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M2401-MN6T View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M2401-MN6T Datasheet PDF : 26 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 9. Read Mode Sequences
CURRENT
ADDRESS
READ
ACK
NO ACK
DEV SEL
DATA OUT
R/W
RANDOM
ADDRESS
READ
ACK
ACK
ACK
NO ACK
DEV SEL *
BYTE ADDR
DEV SEL *
DATA OUT
R/W
R/W
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
ACK
DEV SEL
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
ACK
ACK
ACK
ACK
DEV SEL *
BYTE ADDR
DEV SEL *
DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01942
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
Current Address Read
Read Operations
The device has an internal address counter which
Read operations are performed independently of is incremented each time a byte is read. For the
the state of the Write Control (WC) signal.
Current Address Read operation, following a Start
Random Address Read
A dummy Write is performed to load the address
into the address counter (as shown in Figure 9) but
without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats
the Device Select Code, with the RW bit set to 1.
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master
condition, the bus master only sends a Device Se-
lect Code with the RW bit set to 1. The device ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The bus master terminates the
transfer with a Stop condition, as shown in Figure
9, without acknowledging the byte.
Sequential Read
must not acknowledge the byte, and terminates This operation can be used after a Current Ad-
the transfer with a Stop condition.
dress Read or a Random Address Read. The bus
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