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M2004-02-669.3266 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M2004-02-669.3266
ICST
Integrated Circuit Systems ICST
M2004-02-669.3266 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Micro Networks
An Integrated Circuit Systems Company
M2004-02
Preliminary Specifications
TABLE 2
Pin Number
1, 2, 3
4, 9
5, 8
6, 7
10, 14, 26
11, 19, 33
12, 13
Name
GND
OP_IN, nOP_IN
nOP_OUT, OP_OUT
nVC, VC
GND
VCC
N0, N1
PIN DESCRIPTIONS
I/O
GND
Analog I/O
Analog I/O
Input
GND
Power
Input
Configuration
Pull - down
15, 16
17
FOUT, nFOUT
MR
Output
Input
Unterminated
Pull - down
18, 20, 21
22
NC
REF_SEL
Input
Pull - down
23
NDIF_REF
Input
24
DIF_REF
Input
25
REF_ CLK
Input
27, 28, 29, 30, 31 M0, M1, M2, M3, M4 Input
32
M5
Input
34, 35, 36
DNC
Pull - down
Pull - down
Pull - down
Pull - down
Pull - down
Description
Power Supply Ground
Used for external loop filter. See Figure 2.
Used for external loop filter. See Figure 2
VCSO Differential Control Voltage Input Pair
Power Supply Ground
Positive Supply Pins
Determines the output divider value as
defined in Table 3C. LVCMOS / LVTTL
interface levels.
Differential output, 3.3V LVPECL levels.
Logic HIGH resets the reference frequency and N
output dividers. Logic LOW enables the outputs.
LVCMOS / LVTTL interface levels.
No Connection
Selects between the different reference clock
inputs as the PLL reference source. See table 3D.
LVCMOS / LVTTL interface levels.
Inverting differential clock input. Compatible
logic levels include LVCMOS, LVDS, HSTL, etc.
Non-inverting differential clock input. Compatible
logic levels include LVCMOS, LVDS, HSTL, etc.
Input reference clock. LVCMOS / LVTTL interface
levels.
M divider inputs. Data is always transparent. No
latch signal is required.
Do not connect. Internal test pins.
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
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