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M2004-02-666.5143 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M2004-02-666.5143
ICST
Integrated Circuit Systems ICST
M2004-02-666.5143 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Micro Networks
An Integrated Circuit Systems Company
M2004-02
Preliminary Specifications
FUNCTIONAL BLOCK DIAGRAM
Functional Description:
The internal PLL will adjust the VCSO output
frequency to be M (feedback divider) times the
selected input reference clock frequency. Note that
the product of M x the input reference frequency
OP_IN nOP_IN OP_OUT
nOP_OUT
Vc nVc
DIF_REF 0
nDIF_REF 0
REF_CLK
REF_SEL
M5:M0
MR
Mux
Phase
Detector &
Active Loop
Filter
+M
VCSO
Output
Divider
Parallel Programming Interface
F OUT
nF OUT
N1
The multiplying factor is programmed via a 6-bit
parallel bus.
The relationship between the VCSO frequency, the
M divider, and the Differential Input reference clock
is defined as follows:
F VCSO = F REF_CLK x M
When the N output divider is included, the
complete relationship for the output frequency is
defined as:
FOUT = F VCSO = F REF_CLK x M
N
N
The N1 input can be hard wired to set the N divider
to a specific state that will automatically occur
during power-up.
must be such that it falls within the “lock” range of
the VCSO. The N output divider can be
programmed to divide the VCSO output frequency
by 1, 2, 4, or 8 and provide a 50% output duty
cycle.
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
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