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M2006-12A-669.3266 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M2006-12A-669.3266
ICST
Integrated Circuit Systems ICST
M2006-12A-669.3266 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Integrated
Circuit
Systems, Inc.
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50to VCC - 2V
Symbol Parameter
Min Typ
Max Unit Test Conditions
Input
FIN
Frequency
Range
Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700 MHz
Output
FFOUT Output Frequency
Frequency
Range
FOUT0, nFOUT0,
FOUT1, nFOUT1
100
700
APR VCSO Pull-Range
Commercial
Industrial
±120 ±200
±50 ±150
KVCO VCO Gain
800
PLL Loop
Constants 1
RIN
Internal Loop Resistor
50
BWVCSO VCSO Bandwidth
700
Φ n Single Side Band
1kHz Offset
-72
Phase Noise
and Jitter
J(t)
Phase Noise
@622.08MHz
Jitter (rms)
10kHz Offset
100kHz Offset
12kHz to 20MHz
-94
-123
0.25
0.5
@622.08MHz
50kHz to 80MHz
0.25
0.5
tPW
Output Duty Cycle 2 P0, P1 = 1
FOUT0, nFOUT0,
FOUT1, nFOUT1
P0, P1 = 4
40
50
60
45
50
55
tR
Output Rise Time 2 FOUT0, nFOUT0,
tF
Output Fall Time 2
FOUT1, nFOUT1
200 450
500
200 450
500
Note 1: Parameters needed for PLL Simulator software; see PLL Simulator Tool Available on pg. 5.
Note 2: See Parameter Measurement Information on pg. 8.
MHz
ppm
ppm
kHz/V
k
kHz
dBc/Hz
Fin=19.44 MHz
dBc/Hz Mfin=32, Mfec=1, Rfec=1
dBc/Hz
ps rms
ps rms
%
%
ps
20% to 80%
ps
20% to 80%
Table 12: AC Characteristics
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
20%
Clock Output
80%
tR
80%
VP-P
20%
tF
Figure 5: Output Rise and Fall Time
FOUT
odc =
tPW
tPERIOD
tPW
(Output Pulse Width)
tPERIOD
Figure 6: Output Duty Cycle
M2006-12A Datasheet Rev 1.0
8 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400
 

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