DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

M2006-12A-669.3266 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M2006-12A-669.3266
ICST
Integrated Circuit Systems ICST
M2006-12A-669.3266 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Integrated
Circuit
Systems, Inc.
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
DETAILED BLOCK DIAGRAM
APC
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
M2006-12 A
MUX
0
1
Rfec
Divider
4
FEC_SEL3:0
2
FIN_SEL1:0
Mfec / Rfec
Divider LUT
RLOOP CLOOP
RLOOP CLOOP
RPOST
RPOST
CPOST
CPOST
OP_IN nOP_IN OP_OUT nOP_OUT nVC VC
Phase
Detector
RIN
RIN
Loop Filter
Amplifier
Phase
Locked
Loop
(PLL)
Mfec Divider
Mfin Divider
External
Loop Filter
Components
SAW Delay Line
Phase
Shifter
VCSO
P0 Divider
P = 1 ( P0_SEL = 0 )
or 4 ( P0_SEL = 1 )
Mfin Divider
LUT
P1 Divider
P = 1 ( P1_SEL = 0 )
or 4 ( P1_SEL = 1 )
FOUT0
nFOUT0
FOUT1
nFOUT1
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
11, 19, 33
VCC
12, 13
15, 16
17
18
FOUT1, nFOUT1
FOUT0, nFOUT0
P1_SEL
P0_SEL
20
nDIF_REF1
21
DIF_REF1
22
REF_SEL
23
nDIF_REF0
24
DIF_REF0
25
APC
27
28
29
30
31
32
34, 35, 36
FIN_SEL1
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
DNC
P0_SEL
Figure 3: Detailed Block Diagram
P1_SEL
I/O
Ground
Input
Output
Input
Power
Output
Input
Input
Input
Input
Input
Input
Configuration
Description
Power supply ground connections.
External loop filter connections. See Figure 4.
Power supply connection, connect to +3.3V.
No internal terminator
Clock output pairs. Differential LVPECL.
Internal pull-down resistor1
Internal pull-UP resistor1
Internal pull-down resistor1
Internal pull-down resistor1
Internal pull-UP resistor1
Internal pull-down resistor1
Internal pull-down resistor1
Internal pull-down resistor1
P Divider controls. LVCMOS/LVTTL.
(For P0_SEL, P1_SEL, see Table 6 on pg. 3.
Reference clock input pair 1.
Differential LVPECL or LVDS.
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
Reference clock input pair 0.
Differential LVPECL or LVDS.
Automatic Phase Compensation (phase
build-out). LVCMOS/LVTTL:
Logic 1 - Device absorbs input phase transients.
Logic 0 - Device doesn’t absorb transients.
Input clock frequency selection. LVCMOS/LVTTL.
(For FIN_SEL1:0, see Table 4 on pg. 3.
Input
Internal pull-UP resistor1
FEC PLL divider ratio selection. LVCMOS/ LVTTL.
(For FEC_SEL3:0, see Table 5 on pg. 3.)
Do Not Connect.
Internal nodes. Connection to these pins can
cause erratic device operation.
Table 3: Pin Descriptions
M2006-12A Datasheet Rev 1.0
2 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]