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M2006-02A-669.3120 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M2006-02A-669.3120
ICST
Integrated Circuit Systems ICST
M2006-02A-669.3120 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2006-02A
VCSO BASED FEC CLOCK PLL
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2006-02A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
The device supports both forward
and inverse FEC (Forward Error
Correction) clock multiplication
ratios. Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
Reduced intrinsic output jitter and improved power
supply noise rejection compared to M2006-02
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
28
18
29
17
30
16
31 M 2 0 0 6 - 0 2 A 15
32
14
33
(Top View)
13
34
12
35
11
36
10
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation, including:
• 255/238 (OTU1) Mapping and 238/255 De-mapping
• 255/237 (OTU2) Mapping and 237/255 De-mapping
• 255/236 (OTU3) Mapping and 236/255 De-mapping
Input reference and VCSO frequencies up to 700MHz,
supports loop timing modes
(Specify VCSO frequency at time of order)
Figure 1: Pin Assignment
Example I/O Clock Combinations
Using M2006-02A-622.0800
PLL Ratio Input Clock (MHz) Output Clock (MHz)
Supports active switching between inverse-FEC and
non-FEC clock ratios (same VCSO center frequency)
Ideal for complex ratio FEC ratio translation and
for use with an unstable reference (i.e., similar to the
M2006-12A - and pin-compatible - but without the
Hitless Switching and Phase Build-out functions)
1/1
237/255
(inverse FEC)
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
622.08
or
155.52
Table 1: Example I/O Clock Combinations Using M2006-02A-622.0800
Using M2006-02A-669.3266
Single 3.3V power supply
PLL Ratio Input Clock (MHz) Output Clock (MHz)
Small 9 x 9 mm SMT (surface mount) package
237/255
(FEC rate)
1/1
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
669.3266
or
167.3316
Table 2: Example I/O Clock Combinations Using M2006-02A-669.3266
SIMPLIFIED BLOCK DIAGRAM
M2006-02A
Loop
Filter
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
4
FEC_SEL3:0
2
FIN_SEL1:0
0
Rfec Div
1
VCSO
Mfec Div
Mfin Div
(1, 4, 8, or 32)
Mfec / Rfec
Divider LUT
Mfin Divider
LUT
P0_SEL
Figure 2: Simplified Block Diagram
P0 Div
(1 or 4)
P1 Div
(1 or 4)
P1_SEL
FOUT0
nFOUT0
FOUT1
nFOUT1
M2006-02A Datasheet Rev 1.0
Revised 28Jul2004
M2006-02A VCSO Based FEC Clock PLL
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400
 

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