M16623FG Datasheet PDF -

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Description

Manufacturer

M16623FG

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Mitsubishi microcomputers

M16C / 62A Group (80-pin)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(1) Processor mode register 0

(000416)···

0016

(2) Processor mode register 1

(000516)··· 0 0 0 0 0

(3) System clock control register 0

(000616)··· 0 1 0 0 1 0 0 0

(4) System clock control register 1

(000716)··· 0 0 1 0 0 0 0 0

(5) Chip select control register

(000816)··· 0 0 0 0 0 0 0 1

(6) Address match interrupt enable

(7) Protect register

(8) Watchdog timer control register

(000916)···

(000A16)···

000

(000F16)··· 0 0 0 ? ? ? ? ?

(9) Address match interrupt register 0 (001016)···

0016

(001116)···

0016

(001216)···

00 0 0

(10) Address match interrupt register 1 (001416)···

0016

(001516)···

0016

(001616)···

00 0 0

(11)DMA0 control register

(002C16)··· 0 0 0 0 0 ? 0 0

(12)DMA1 control register

(003C16)··· 0 0 0 0 0 ? 0 0

(13) INT3 interrupt control register

(004416)···

0 0 ? 00 0

(14)Timer B5 interrupt control register (004516)···

?000

(15)Timer B4 interrupt control register (004616)···

?000

(16)Timer B3 interrupt control register (004716)···

?0 0 0

(17) SI/O4 interrupt control register

(004816)···

00 ? 0 0 0

(18) SI/O3 interrupt control register

(19)Bus collision detection interrupt

control register

(20) DMA0 interrupt control register

(004916)···

(004A16)···

(004B16)···

(21) DMA1 interrupt control register

(004C16)···

(22) Key input interrupt control register (004D16)···

0 0 ?0 0 0

?0 0 0

(23) A-D conversion interrupt control

(24) UART2 transmit interrupt control

(25) UART2 receive interrupt control

(26) UART0 transmit interrupt control

(27) UART0 receive interrupt control

(004E16)···

(004F16)···

(005016)···

(005116)···

(005216)···

?0 0 0

?000

(28) UART1 transmit interrupt control register

(29) UART1 receive interrupt control register

(30)Timer A0 interrupt control register

(31) Timer A1 interrupt control register

(32)Timer A2 interrupt control register

(33) Timer A3 interrupt control register

(005316)···

(005416)···

(005516)···

(005616)···

(005716)···

(005816)···

?000

(34)Timer A4 interrupt control register

(35)Timer B0 interrupt control register

(36) Timer B1 interrupt control register

(37)Timer B2 interrupt control register

(38) INT0 interrupt control register

(39) INT1 interrupt control register

(40) INT2 interrupt control register

(41)Timer B3,4,5 count start flag

(42)Three-phase PWM control register 0

(005916)···

?000

(005A16)···

?000

(005B16)···

?000

(005C16)···

?000

(005D16)···

00?000

(005E16)···

00?000

(005F16)···

00?000

(034016)··· 0 0 0

(034816)···

0016

(43)Three-phase PWM control register 1

(034916)···

0016

(44) Three-phase output buffer register 0

(034A16)···

0016

(45) Three-phase output buffer register 1

(034B16)···

0016

(46)Timer B3 mode register

(035B16)··· 0 0 ? ? 0 0 0 0

(47) Timer B4 mode register

(035C16)··· 0 0 ? 0 0 0 0

(48) Timer B5 mode register

(49)Interrupt cause select register

(035D16)··· 0 0 ? 0 0 0 0

(035F16)···

0016

(50) SI/O3 control register

(036216)···

4016

(51) SI/O4 control register

(036616)···

4016

(52)UART2 special mode register 3 (Note)

(53) UART2 special mode register 2

(54)UART2 special mode register

(037516)···

(037616)···

(037716)···

0016

(55) UART2 transmit/receive mode register

(037816)···

0016

(56)UART2 transmit/receive control register 0 (037C16)··· 0 0 0 0 1 0 0 0

(57)UART2 transmit/receive control register 1 (037D16)··· 0 0 0 0 0 0 1 0

x : Nothing is mapped to this bit

? : Undefined

The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set.

The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM,

the value may be set as unknown due to the termination of the CPU access.

Note: “0016” is read out when set bit 7 (SDDS) of the UART2 special mode register (address 037716) to “1”.

Figure 1.6.3. Device's internal status after a reset is cleared

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