M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
About the M16C/62N (80-pin version) group
The M16C/62N (80-pin version) group is packaged in a 80-pin plastic mold package. The number of pins
in comparison with the 100-pin package products is decreased. So be careful about the following.
(a) The M16C/62N (80-pin version) group supports single chip mode alone. It supports neither
memory expansion mode nor microprocessor mode.
(b) The input/output ports given below are absent from the M16C/62N (80-pin version) group. To
stabilize the internal state, set to output mode the direction register of each input/output port. Fail-
ing in setting to output mode involves an increase in current consumption.
<Pins absent from the 80-pin version>
P10 to P17, P44 to P47, P72 to P75, P91
(c) INT3 to INT5 allocated to P15 to P17 cannot be used. Keep the INT3 interrupt control register
disabled for interrupts. The INT4 interrupt control register and the INT5 interrupt control register
are shared with SI/O3 and SI/O4. When the user don’t use them as SI/O3 and SI/O4, set them
disabled for interrupts.
(d) The output pins of timers A1 and A2 - TA1IN, TA1OUT, TA2IN and TA2OUT - allocated to P72 to P75
cannot be used. In connection with this, the gate function and pulse outputting function of timers A1
and A2 cannot be used. Use timer mode and internal event count, or use as trigger signal genera-
tion in one-shot timer mode.
(e) The UART2 input/output pins - CLK2 and CTS2/RTS2 - allocated to P72 and P73 cannot be used.
In connection with this, UART2 solely as UART of the internal clock can be used. And UART2 must
be used by setting the CTS/ RTS disable bit (bit 4 at address 037C16) to “1”.
(f) The input pin TB1IN of timer B1 allocated to P91 cannot be used. With timer B1 under this state, use
only timer mode or the internal event count.
(g) The input pin SIN3 of serial I/O3 allocated to P91 cannot be used. In connection with this, use serial
I/O3 as a serial I/O exclusive to transmission.
(h) The output pins for three-phase motor control allocated to P72 to P75 cannot be used. So set to 0
(ordinary mode) the mode select bit (bit 2) of three-phase PWM control register 0.
(i) The registers given below are reserved registers. Do not access these registers for read or write.
000816 Chip select control register (CSR)
034B16 Thrree-phase output buffer register 1(IDB1)
000B16 Data bank register (DBR)
034916 Three-phase PWM control register 1(INVC1)
034A16 Thrree-phase output buffer register 0(IDB0)
034C16 Dead time timer(DTT)
034D16 Timer B2 interrupt occurrence frequency set
03FF16 Port control register (PCR)