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M14C16-WS41 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
M14C16-WS41 Memory Card IC 16/4 Kbit Serial I²C Bus EEPROM ST-Microelectronics
STMicroelectronics ST-Microelectronics
M14C16-WS41 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
First byte of instruction
with RW = 0 already
decoded by M14xxx
NO ACK
Returned
YES
Next
NO
Operation is
Addressing the
Memory
ReSTART
YES
Send
Byte Address
STOP
M14C16, M14C04
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI02165
with an ACK, indicating that the memory is
ready to receive the second part of the next in-
struction (the first byte of this instruction having
been sent during Step 1).
Read Operations
Read operations are independent of the state of
the WC pin. On delivery, the memory content is set
at all “1’s” (FFh).
Current Address Read
The memory has an internal address counter.
Each time a byte is read, this counter is increment-
ed. For the Current Address Read mode, following
a START condition, the master sends a device se-
lect with the RW bit set to ‘1’. The memory ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The master must not acknowl-
edge the byte output, and terminates the transfer
with a STOP condition, as shown in Figure 8.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
This is followed by another START condition from
the master and the device select is repeated with
the RW bit set to ‘1’. The memory acknowledges
this, and outputs the byte addressed. The master
must not acknowledge the byte output, and termi-
nates the transfer with a STOP condition.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. How-
ever, in this case the master does acknowledge
the data byte output, and the memory continues to
output the next byte in sequence. To terminate the
stream of bytes, the master must not acknowledge
the last byte output, and must generate a STOP
condition. The output data comes from consecu-
tive addresses, with the internal address counter
automatically incremented after each byte output.
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