LTC3200 View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC3200

Low Noise, Regulated Charge Pump DC/DC Converters

Linear Technology 

U

OPERATIO

LTC3200/LTC3200-5

Power Efficiency

The power efficiency (η) of the LTC3200/LTC3200-5 is

similar to that of a linear regulator with an effective input

voltage of twice the actual input voltage. This occurs

because the input current for a voltage doubling charge

pump is approximately twice the output current. In an ideal

regulating voltage doubler the power efficiency would be

given by:

η ≡ POUT = VOUT •IOUT = VOUT

PIN VIN • 2IOUT 2VIN

At moderate to high output power the switching losses

and quiescent current of the LTC3200/LTC3200-5 are

negligible and the expression above is valid. For example

with VIN = 3V, IOUT = 50mA and VOUT regulating to 5V the

measured efficiency is 80% which is in close agreement

with the theoretical 83.3% calculation.

Operation at VIN > 5V

LTC3200/LTC3200-5 will continue to operate with input

voltages somewhat above 5V. However, because of its

constant frequency nature, some charge due to internal

switching will be coupled to VOUT causing a slight upward

movement of the output voltage at very light loads. To

avoid an output overvoltage problem with high VIN, a

moderate standing load current of 1mA will help the

LTC3200/LTC3200-5 maintain exceptional line regula-

tion. This can be achieved with a 5k resistor from VOUT to

GND.

Layout Considerations

Due to its high switching frequency and the high transient

currents produced by the LTC3200/LTC3200-5, careful

board layout is necessary. A true ground plane and short

connections to all capacitors will improve performance and

ensure proper regulation under all conditions. Figure 5

shows an example layout for the LTC3200-5.

Thermal Management

For higher input voltages and maximum output current

there can be substantial power dissipation in the LTC3200/

LTC3200-5. If the junction temperature increases above

approximately 160°C the thermal shutdown circuitry will

automatically deactivate the output. To reduce the

maximum junction temperature, a good thermal connec-

tion to the PC board is recommended. Connecting the

GND pin (Pins 4/5 for LTC3200, Pin 2 for LTC3200-5) to

a ground plane, and maintaining a solid ground plane

under the device on two layers of the PC board can reduce

the thermal resistance of the package and PC board

considerably.

Derating Power at Higher Temperatures

To prevent an overtemperature condition in high power

applications Figure 6 should be used to determine the

maximum combination of ambient temperature and power

dissipation.

1.2

θJA = 175°C/W

TJ = 160°C

1.0

VIN

VOUT

1µF

GND

SHDN

LTC3200-5

1µF

1µF

32005 F03

Figure 5. Recommended Layout

0.8

0.6

0.4

0.2

0

–50

–25 0 25 50 75 100

AMBIENT TEMPERATURE (°C)

32005 • F06

Figure 6. Maximum Power Dissipation

vs Ambient Temperature

9

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