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LP0701ND View Datasheet(PDF) - Supertex Inc

Part NameLP0701ND Supertex
Supertex Inc Supertex
DescriptionP-Channel Enhancement-Mode Lateral MOSFET
LP0701ND Datasheet PDF : 6 Pages
1 2 3 4 5 6
8-Lead SOIC (Narrow Body) Package Outline (LG)
D
θ1
8
LP0701
Note 1
(Index Area
D/2 x E1/2)
E1 E
L2
Gauge
Plane
1
Top View
A A2
A1
Seating
Plane
e
b
Side View
Note 1
h
L
θ
L1
View B
h
Seating
Plane
View B
View A-A
Note:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
Symbol
A
A1 A2
b
D
E
E1
e
h
L
L1 L2
θ θ1
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
0.25 0.40
0O 5O
Dimension
(mm)
NOM
-
-
-
-
4.90
6.00
3.90
1.27
BSC
-
-
1.04 0.25
REF BSC
-
-
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00*
0.50 1.27
8O 15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.
Doc.# DSFP-LP0701
B071513
Supertex inc.
5
www.supertex.com
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