LPC1315FBD48 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC1315FBD48

32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM

NXP Semiconductors. 

NXP Semiconductors

LPC1315/16/17/45/46/47

32-bit ARM Cortex-M3 microcontroller

• Software interrupt generation.

7.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

7.7 IOCON block

The IOCON block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7.1 Features

• Programmable pull-up, pull-down, or repeater mode.

• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their

pull-up resistor is enabled.

• Programmable pseudo open-drain mode.

• Programmable 10-ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to

PIO0_16. The glitch filter is turned off by default.

• Programmable hysteresis.

• Programmable input inverter.

7.8 General Purpose Input/Output GPIO

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

LPC1315/16/17/45/46/47 use accelerated GPIO functions:

• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achieved.

• Entire port value can be written in one instruction.

Any GPIO pin providing a digital function can be programmed to generate an interrupt on

a level, a rising or falling edge, or both.

The GPIO block consists of three parts:

1. The GPIO ports.

2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.

3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO

pins.

LPC1315_16_17_45_46_47

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 20 September 2012

© NXP B.V. 2012. All rights reserved.

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