LPC1315FBD48 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC1315FBD48

32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM

NXP Semiconductors. 

LPC1315/16/17/45/46/47

32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash;

up to 12 kB SRAM; USB device; USART; EEPROM

Rev. 3 — 20 September 2012

Product data sheet

1. General description

The LPC1315/16/17/45/46/47 are ARM Cortex-M3 based microcontrollers for embedded

applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced

debug features and a higher level of support block integration.

The LPC1315/16/17/45/46/47 operate at CPU frequencies of up to 72 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller

available on the LPC1345/46/47, this series brings unparalleled design flexibility and

seamless integration to today’s demanding connectivity solutions.

The peripheral complement of the LPC1315/16/17/45/46/47 includes up to 64 kB of flash

memory, 8 kB or 10 kB of SRAM data memory, one Fast-mode Plus I2C-bus interface, one

RS-485/EIA-485 USART with support for synchronous mode and smart card interface,

two SSP interfaces, four general purpose counter/timers, an 8-channel, 12-bit ADC, and

up to 51 general purpose I/O pins.

2. Features and benefits

 System:

 ARM Cortex-M3 r2p1 processor, running at frequencies of up to 72 MHz.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Non Maskable Interrupt (NMI) input selectable from several input sources.

 System tick timer.

 Memory:

 Up to 64 kB on-chip flash program memory with a 256 byte page erase function.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software. Flash updates via USB supported.

 Up to 4 kB on-chip EEPROM data memory with on-chip API support.

 Up to 12 kB SRAM data memory.

 16 kB boot ROM with API support for USB API, power control, EEPROM, and flash

IAP/ISP.

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