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ST92124JCV9Q6 Ver la hoja de datos (PDF) - STMicroelectronics

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ST92124JCV9Q6 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST92124JCV9Q6 Datasheet PDF : 429 Pages
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ST92F124/F150/F250 - KNOWN LIMITATIONS
13.8.9 SCI-A wrong break duration
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a
longer duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than ex-
pected.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit fre-
quency of 19200 baud (fCPU=8MHz and
SCIBRR=0xC9), the wrong break duration occur-
rence is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
LIN mode (if available)
If the LINE bit in the SCICR3 is set and the M bit in
the SCICR1 register is reset, the SCI-A is in LIN
master mode. A single break character is sent by
setting and resetting the SBK bit in the SCICR2
register. In some cases, the break character may
have a longer duration than expected:
- 24 bits instead of 13 bits
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