ST92124JCV1TB View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92124JCV1TB
STMicroelectronics
ST92124JCV1TB Datasheet PDF : 429 Pages
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ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
13.8 EMULATION CHIP LIMITATIONS
Additional limitations exist on Emulation chips (EMU2 emulator). These limitations correspond to those
present in AxxxxxxxxY trace codes (ST92F150). They are listed in the following table.
Section
Section 13.8.1
Section 13.8.2
Section 13.8.3
Section 13.8.4
Section 13.8.5
Section 13.8.6
Section 13.8.7
Section 13.8.8
Section 13.8.9
Section 13.8.10
Section 13.8.11
Limitation (AxxxxxxxxY trace code)
RESET BEHAVIOUR FOR BI-DIRECTIONAL, WEAK PULL-UP PORTS
HIGH DRIVE I/Os WHEN BSZ=1
ADC PARASITIC DIODE
ADC ACCURACY VS. NEGATIVE INJECTION CURRENT
I2CECCR REGISTER LIMITATION
I2C BEHAVIOUR DISTURBED DURING DMA TRANSACTIONS
MFT DMA MASK BIT RESET
DMA DATA CORRUPTED BY MFT INPUT CAPTURE
SCI-A WRONG BREAK DURATION
LIN MASTER MODE NOT PRESENT ON SCI-A
LIMITATIONS ON LQFP64 PACKAGES
13.8.1 RESET BEHAVIOUR FOR BI-
DIRECTIONAL, WEAK PULL-UP PORTS
This section applies to ports P1[7:3], P4[1], P8[7:2]
and P9[7:0].
During the reset phase (external reset signal low)
and the delay of 20400 clock periods (tRSPH) fol-
lowing a reset, these ports are in High Impedance
state, while according to the datasheet they should
Table 76. Reset Behaviour Table
have weak pull-ups. These ports then enter Weak
Pull-up state until the user overwrites the reset
values of I/O Port Control Registers PxC0, PxC1
and PxC2.
Port
P1[7:3]
P4.1
P8[7:2]
P9[7:0]
Rev Z Behaviour
Datasheet
Condition
Port Behaviour
While RESET
is low
During next
20K Clock
Cycles
After these
20K Clock
Cycles
Bi-Dir + WPU
Hi-Z
Hi-Z
Bi-Dir + WPU
Bi-Dir + WPU
Hi-Z
Hi-Z
Bi-Dir + WPU
Bi-Dir + WPU
Hi-Z
Hi-Z
Bi-Dir + WPU
Bi-Dir + WPU
Hi-Z
Hi-Z
Bi-Dir + WPU
Control Register Value
PxC0 PxC1 PxC2
0
0
0
0
0
0
0
0
0
0
0
0
Shaded areas represent erroneous operations.
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