ST92124CV2Q6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92124CV2Q6

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

Impact On Apllication

1. The MFT1 wins the next DMA Arbitration, the

DMA request is serviced.

The MFT0 interrupt routine is executed before

the next Input Capture or Output Compare

event. It detects that a wrong Mask Bit Reset

has occurred on the MFT1 and re-enables the

DMA Mask.

=> There is no application impact.

2. The MFT1 does not win the next DMA Arbitra-

tion, the DMA request is not serviced. The

MFT1 will not request the DMA again as its

DMA Mask bit is reset.

=> A DMA transfer is lost.

The MFT0 interrupt routine is executed be-

fore the next Input Capture or Output Com-

pare event. It detects that a wrong Mask Bit

Reset has occurred on the MFT1 and re-ena-

bles the DMA Mask.

=> An Input Capture value is lost or a Com-

pare value is used twice.

3. The MFT1 wins the next DMA Arbitration, the

DMA request is serviced.

The MFT0 interrupt routine is not executed

before the next MFT1 Input Capture or Output

Compare event. This new event generates an

Interrupt. The interrupt routine must check

that the DMA counter is equal to 0. If it is not

equal to 0, the DMA counter and address

must not be changed, but the DMA Mask

must be set.

=> An Input Capture value or a Comparison

value must be handled by the interrupt rou-

tine.

If this failure recovery management can be

executed fast enough within the interrupt rou-

tine, there is no impact on the application.

Otherwise the counter will reach the new

compare value before it has been loaded in

the Compare Register or a new input capture

event will occur before the previous value has

been saved.

4. The MFT1 does not win the next DMA Arbi-

tration, the DMA request is not serviced. The

MFT1 will not request the DMA again as its

DMA Mask bit is reset.

=> A DMA transfer is lost.

The MFT0 interrupt routine is not executed

before the next MFT1 Input Capture or Output

Compare event. This new event generates an

Interrupt. The interrupt routine must check

that the DMA counter is equal to 0. If it is not

equal to 0, the DMA counter and address

must not be changed, but the DMA Mask

must be set.

=> An Input Capture value or a Comparison

value must be handled by the interrupt rou-

tine.

If this failure recovery management can be

executed fast enough within the interrupt rou-

tine, only one transfer is lost. Otherwise the

counter will reach the new compare value

before it has been loaded in the Compare

Register or a new input capture event will

occur before the previous value has been

saved.

Workaround

If it is not possible to limit the DMA to one MFT

only (no DMA with another MFT, SCI-M or I2C),

the following failure recovery management must

be included in the MFT, SCI-M, I2C Interrupt rou-

tines (if the DMA is used).

1. Following an End-of-Block event (DMA coun-

ter equal to 0):

Check the other MFT DMA counter (both

MFTs if this is the SCI-M or the I2C interrupt

routine). If the counter does not equal 0 and

the DMA mask is reset, reset the interrupt flag

bit, set the DMA Mask bit.

2. Following an Input Capture or an Output

Compare event (DMA counter does not equal

0):

Execute the transfer by software, modify the

DMA counter and address, reset the interrupt

flag bit, set the DMA Mask bit.

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