ST92124DV9QC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92124DV9QC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

13.3 I2C LIMITATIONS

Limitations

Section 13.3.1

Section 13.3.2

Section 13.3.3

Section 13.3.4

Section 13.3.5

Section 13.3.6

Description

Start condition ignored

Missing bus error

AF bit (acknowledge failure flag)

BUSY bit

ARLO (arbitration lost)

BUSY flag

Mode

Mustimaster mode

Master transmitter mode

Transmitter mode (Master and Slave)

Mustimaster mode

Multimaster mode

All

13.3.1 Start condition ignored in multimaster mode

Description

Multimaster Mode:

In multimaster configurations, if the ST9 I2C re-

ceives a START condition from another I2C

master after the START bit is set in the I2CCR reg-

ister and before the START condition is generated

by the ST9 I2C, it may ignore the START condition

from the other I2C master. In this case, the ST9

master will receive a NACK from the other device.

Normally the BERR bit would be set whenever un-

authorized transmission takes place while transfer

is already in progress. However, an issue will arise

if an external master generates an unauthorized

Start or Stop while the I2C master is on the first or

second pulse of a 9-bit transaction.

Workaround

On reception of the NACK, ST9 can send a re-start

and Slave address to re-initiate communication.

13.3.2 Missing BUS error in master transmitter

mode

Description

Workaround

Single Master Mode:

Slave devices should issue a NACK when they re-

ceive a misplaced Start or Stop. The reception of a

NACK or BUSY by the master in the middle of

communication gives the possibility to reinitiate

transmission.

BERR will not be set if an error is detected during

the first or second pulse of each 9-bit transaction.

Single Master Mode:

If a Start or Stop is issued during the first or

second pulse of a 9-bit transaction, the BERR flag

will not be set and transfer will continue however

the BUSY flag will be reset.

Multimaster Mode:

It is possible to work around the problem by polling

the BUSY bit during I2C master mode transmis-

sion. The resetting of the BUSY bit can then be

handled in a similar manner as the BERR flag

being set.

411/429

1

Share Link: