ST92124JCV9TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92124JCV9TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - DEVICE ARCHITECTURE

SYSTEM REGISTERS (Cont’d)

2.3.2 Flag Register

The Flag Register contains 8 flags which indicate

the CPU status. During an interrupt, the flag regis-

ter is automatically stored in the system stack area

and recalled at the end of the interrupt service rou-

tine, thus returning the CPU to its original status.

This occurs for all interrupts and, when operating

in nested mode, up to seven versions of the flag

register may be stored.

FLAG REGISTER (FLAGR)

R231- Read/Write

Register Group: E (System)

Reset value: 0000 0000 (00h)

7

0

C

Z

S

V DA H

- DP

Bit 7 = C: Carry Flag.

The carry flag is affected by:

Addition (add, addw, adc, adcw),

Subtraction (sub, subw, sbc, sbcw),

Compare (cp, cpw),

Shift Right Arithmetic (sra, sraw),

Shift Left Arithmetic (sla, slaw),

Swap Nibbles (swap),

Rotate (rrc, rrcw, rlc, rlcw, ror,

rol),

Decimal Adjust (da),

Multiply and Divide (mul, div, divws).

When set, it generally indicates a carry out of the

most significant bit position of the register being

used as an accumulator (bit 7 for byte operations

and bit 15 for word operations).

The carry flag can be set by the Set Carry Flag

(scf) instruction, cleared by the Reset Carry Flag

(rcf) instruction, and complemented by the Com-

plement Carry Flag (ccf) instruction.

Bit 6 = Z: Zero Flag. The Zero flag is affected by:

Addition (add, addw, adc, adcw),

Subtraction (sub, subw, sbc, sbcw),

Compare (cp, cpw),

Shift Right Arithmetic (sra, sraw),

Shift Left Arithmetic (sla, slaw),

Swap Nibbles (swap),

Rotate (rrc, rrcw, rlc, rlcw, ror,

rol),

Decimal Adjust (da),

Multiply and Divide (mul, div, divws),

Logical (and, andw, or, orw, xor,

xorw, cpl),

Increment and Decrement (inc, incw, dec,

decw),

Test (tm, tmw, tcm, tcmw, btset).

In most cases, the Zero flag is set when the contents

of the register being used as an accumulator be-

come zero, following one of the above operations.

Bit 5 = S: Sign Flag.

The Sign flag is affected by the same instructions

as the Zero flag.

The Sign flag is set when bit 7 (for a byte opera-

tion) or bit 15 (for a word operation) of the register

used as an accumulator is one.

Bit 4 = V: Overflow Flag.

The Overflow flag is affected by the same instruc-

tions as the Zero and Sign flags.

When set, the Overflow flag indicates that a two's-

complement number, in a result register, is in er-

ror, since it has exceeded the largest (or is less

than the smallest), number that can be represent-

ed in two’s-complement notation.

Bit 3 = DA: Decimal Adjust Flag.

The DA flag is used for BCD arithmetic. Since the

algorithm for correcting BCD operations is differ-

ent for addition and subtraction, this flag is used to

specify which type of instruction was executed

last, so that the subsequent Decimal Adjust (da)

operation can perform its function correctly. The

DA flag cannot normally be used as a test condi-

tion by the programmer.

Bit 2 = H: Half Carry Flag.

The H flag indicates a carry out of (or a borrow in-

to) bit 3, as the result of adding or subtracting two

8-bit bytes, each representing two BCD digits. The

H flag is used by the Decimal Adjust (da) instruc-

tion to convert the binary result of a previous addi-

tion or subtraction into the correct BCD result. Like

the DA flag, this flag is not normally accessed by

the user.

Bit 1 = Reserved bit (must be 0).

Bit 0 = DP: Data/Program Memory Flag.

This bit indicates the memory area addressed. Its

value is affected by the Set Data Memory (sdm)

and Set Program Memory (spm) instructions. Re-

fer to the Memory Management Unit for further de-

tails.

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