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ST92124JCV2TC データシートの表示(PDF) - STMicroelectronics

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ST92124JCV2TC 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST92124JCV2TC Datasheet PDF : 429 Pages
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ST92F124/F150/F250 - GENERAL DESCRIPTION
1.6 OPERATING MODES
To optimize the performance versus the power
consumption of the device, the ST92F124/F150/
F250 supports different operating modes that can
be dynamically selected depending on the per-
formance and functionality requirements of the ap-
plication at a given moment.
RUN MODE: This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
SLOW MODE: Power consumption can be signifi-
cantly reduced by running the CPU and the pe-
ripherals at reduced clock speed using the CPU
Prescaler and CCU Clock Divider.
WAIT FOR INTERRUPT MODE: The Wait For In-
terrupt (WFI) instruction suspends program exe-
cution until an interrupt request is acknowledged.
During WFI, the CPU clock is halted while the pe-
ripheral and interrupt controller keep running at a
frequency depending on the CCU programming.
LOW POWER WAIT FOR INTERRUPT MODE:
Combining SLOW mode and Wait For Interrupt
mode it is possible to reduce the power consump-
tion by more than 80%.
STOP MODE: When the STOP is requested by
executing the STOP bit writing sequence (see
dedicated section on Wake-up Management Unit
paragraph), and if NMI is kept low, the CPU and
the peripherals stop operating. Operations resume
after a wake-up line is activated (16 wake-up lines
plus NMI pin). See the RCCU and Wake-up Man-
agement Unit paragraphs in the following for the
details. The difference with the HALT mode con-
sists in the way the CPU exits this state: when the
STOP is executed, the status of the registers is re-
corded, and when the system exits from the STOP
mode the CPU continues the execution with the
same status, without a system reset.
When the MCU enters STOP mode the Watchdog
stops counting. After the MCU exits from STOP
mode, the Watchdog resumes counting from
where it left off.
When the MCU exits from STOP mode, the oscil-
lator, which was sleeping too, requires about 5 ms
to restart working properly (at a 4 MHz oscillator
frequency). An internal counter is present to guar-
antee that all operations after exiting STOP Mode,
take place with the clock stabilised.
The counter is active only when the oscillation has
already taken place. This means that 1-2 ms must
be added to take into account the first phase of the
oscillator restart.
In STOP mode, the oscillator is stopped. There-
fore, if the PLL is used to provide the CPU clock
before entering STOP mode, it will have to be se-
lected again when the MCU exits STOP mode.
HALT MODE: When executing the HALT instruc-
tion, and if the Watchdog is not enabled, the CPU
and its peripherals stop operating and the status of
the machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
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