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ST92124JDR9TC Ver la hoja de datos (PDF) - STMicroelectronics

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ST92124JDR9TC Datasheet PDF : 429 Pages
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AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the begin-
ning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (RW), and
Data signals are valid for memory transfers.
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a
write cycle, data out is valid at the leading edge of
DS. During a read cycle, Data In must be valid pri-
or to the trailing edge of DS. When the ST9 ac-
cesses on-chip memory, DS is held high during
the whole memory cycle.
RESET. Reset (input, active low). The ST9 is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
RW. Read/Write (output, 3-state). Read/Write de-
termines the direction of data transfer for external
memory transactions. RW is low when writing to
external memory, and high for all other transac-
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal, or
an external source to the on-chip clock oscillator
and buffer. OSCIN is the input of the oscillator in-
verter; OSCOUT is the output of the oscillator in-
HW0SW1. When connected to VDD through a 1K
pull-up resistor, the software watchdog option is
selected. When connected to VSS through a 1K
pull-down resistor, the hardware watchdog option
is selected.
VPWO. This pin is the output line of the J1850 pe-
ripheral (JBLPD). It is available only on some de-
RX1/WKUP6. Receive Data input of CAN1 and
Wake-up line 6. Available only on some devices.
When the CAN1 peripheral is disabled, a pull-up
resistor is connected internally to this pin.
TX1. Transmit Data output of CAN1. Available on
some devices.
P0[7:0], P1[7:0] or P9[7:2] (Input/Output, TTL or
CMOS compatible). 11 lines (64-pin devices) or 22
lines (100-pin devices) providing the external
memory interface for addressing 2K or 4M bytes of
external memory.
P0[7:0], P1[2:0], P2[7:0], P3[7:4], P4.[7:4],
P5[7:0], P6[5:2,0], P7[7:0] I/O Port Lines (Input/
Output, TTL or CMOS compatible). I/O lines
grouped into I/O ports of 8 bits, bit programmable
under software control as general purpose I/O or
as alternate functions.
P1[7:3], P3[3:1], P4[3:0], P6.1, P8[7:0], P9[7:0]
Additional I/O Port Lines available on 100-pin ver-
sions only.
P3.0, P6[7:6] Additional I/O Port Lines available
on ST92F250 version only.
AVDD. Analog VDD of the Analog to Digital Con-
verter (common for ADC 0 and ADC 1).
AVDD can be switched off when the ADC is not in
AVSS. Analog VSS of the Analog to Digital Con-
verter (common for ADC 0 and ADC 1).
VDD. Main Power Supply Voltage. Four pins are
available on 100-pin versions, two on 64-pin ver-
sions. The pins are internally connected.
VSS. Digital Circuit Ground. Four pins are availa-
ble on 100-pin versions, two on 64-pin versions.
The pins are internally connected.
VTEST Power Supply Voltage for Flash test pur-
poses. This pin must be kept to 0 in user mode.
VREG. Stabilization capacitors for the internal volt-
age regulator. The user must connect external sta-
bilization capacitors to these pins. Refer to Figure
1.2.1 I/O Port Alternate Functions
Each pin of the I/O ports of the ST92F124/F150/
F250 may assume software programmable Alter-
nate Functions as shown in Section 1.4.
1.2.2 Termination of Unused Pins
For unused pins, input mode is not recommended.
These pins must be kept at a fixed voltage using
the output push pull mode of the I/O or an external
pull-up or pull-down resistor.
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