LMV321 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
LMV321 Datasheet PDF : 16 Pages
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DATA SHEET
LMV321/LMV358/LMV324
LMV358 Package Dimensions
SOIC
D
e
CL
ZD
CL E H
Pin No. 1
B
A A1
DETAIL-A
h x 45°
A2
α
7°
L
DETAIL-A
C
SYMBOL
A1
B
C
D
E
e
H
h
L
A
ZD
A2
SOIC-8
MIN
MAX
0.10
0.25
0.36
0.46
0.19
0.25
4.80
4.98
3.81
3.99
1.27 BSC
5.80
6.20
0.25
0.50
0.41
1.27
1.52
1.72
0
8
0.53 ref
1.37
1.57
NOTE:
1. All dimensions are in millimeters.
2. Lead coplanarity should be 0 to 0.10mm (.004") max.
3. Package surface finishing:
(2.1) Top: matte (charmilles #18~30).
(2.2) All sides: matte (charmilles #18~30).
(2.3) Bottom: smooth or matte (charmilles #18~30).
4. All dimensions excluding mold flashes and end flash
from the package body shall not exceed o.152mm (.006)
per side(d).
MSOP
e
S
E/2 2X
E1 3 7
t2
–H–
Gauge
Plane
E3
E4
aaa A
12
2
46
D2
b
bbb M A B C
D
34
–B– 2
ccc A B C
A2
A
–A–
A1
0.25mm
b
c
c1
b1
Section A - A
5
A
A
02
t1
R1
R
03
L
01
L1
Detail A
Scale 40:1
Detail A
E2
E1
E
NOTE:
1 All dimensions are in millimeters (angle in degrees), unless otherwise specified.
2 Datums – B – and – C – to be determined at datum plane – H – .
3 Dimensions "D" and "E1" are to be determined at datum – H – .
4 Dimensions "D2" and "E2" are for top package and dimensions "D" and "E1" are for bottom package.
5 Cross sections A – A to be determined at 0.13 to 0.25mm from the leadtip.
6 Dimension "D" and "D2" does not include mold flash, protrusion or gate burrs.
7 Dimension "E1" and "E2" does not include interlead flash or protrusion.
MSOP-8
SYMBOL MIN
MAX
A
1.10
–
A1
0.10
±0.05
A2
0.86
±0.08
D
3.00
±0.10
D2
2.95
±0.10
E
4.90
±0.15
E1
3.00
±0.10
E2
2.95
±0.10
E3
0.51
±0.13
E4
0.51
±0.13
R
0.15 +0.15/-0.06
R1
0.15 +0.15/-0.06
t1
0.31
±0.08
t2
0.41
±0.08
b
0.33 +0.07/-0.08
b1
0.30
±0.05
c
0.18
±0.05
c1
0.15 +0.03/-0.02
01
3.0°
±3.0°
02
12.0°
±3.0°
03
12.0°
±3.0°
L
0.55
±0.15
L1
0.95 BSC
–
aaa
0.10
–
bbb
0.08
–
ccc
0.25
–
e
0.65 BSC
–
S
0.525 BSC
–
14
Rev. 1 November 2002
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