Application Information (Continued)
In this example, in order to maintain a 2% peak-to-peak
output voltage ripple and a 40% peak-to-peak inductor cur-
rent ripple, the required maximum ESR is 20 mΩ. The Sanyo
4SP560M electrolytic capacitor will give an equivalent ESR
of 14 mΩ. The capacitance of 560 µF is enough to supply
energy even to meet severe load transient demands.
Selection of the power MOSFETs is governed by a trade-off
between cost, size, and efficiency. One method is to deter-
mine the maximum cost that can be endured, and then
select the most efficient device that fits that price. Breaking
down the losses in the high-side and low-side MOSFETs and
then creating spreadsheets is one way to determine relative
efficiencies between different MOSFETs. Good correlation
between the prediction and the bench result is not guaran-
teed, however. Single-channel buck regulators that use a
controller IC and discrete MOSFETs tend to be most efficient
for output currents of 2 to 10A.
Losses in the high-side MOSFET can be broken down into
conduction loss, gate charging loss, and switching loss.
Conduction, or I2R loss, is approximately:
PC = D (IO2 x RDSON-HI x 1.3)
PC = (1 - D) x (IO2 x RDSON-LO x 1.3)
In the above equations the factor 1.3 accounts for the in-
crease in MOSFET RDSON due to heating. Alternatively, the
1.3 can be ignored and the RDSON of the MOSFET estimated
using the RDSON Vs. Temperature curves in the MOSFET
Gate charging loss results from the current driving the gate
capacitance of the power MOSFETs, and is approximated
PGC = n x (VDD) x QG x fSW
where ‘n’ is the number of MOSFETs (if multiple devices
have been placed in parallel), VDD is the driving voltage (see
MOSFET Gate Drivers section) and QGS is the gate charge
of the MOSFET. If different types of MOSFETs are used, the
‘n’ term can be ignored and their gate charges simply
summed to form a cumulative QG. Gate charge loss differs
from conduction and switching losses in that the actual
dissipation occurs in the LM2745/8, and not in the MOSFET
Switching loss occurs during the brief transition period as the
high-side MOSFET turns on and off, during which both cur-
rent and voltage are present in the channel of the MOSFET.
It can be approximated as:
PSW = 0.5 x VIN x IO x (tr + tf) x fSW
where tr and tf are the rise and fall times of the MOSFET.
Switching loss occurs in the high-side MOSFET only.
For this example, the maximum drain-to-source voltage ap-
plied to either MOSFET is 3.6V. The maximum drive voltage
at the gate of the high-side MOSFET is 3.1V, and the maxi-
mum drive voltage for the low-side MOSFET is 3.3V. Due to
the low drive voltages in this example, a MOSFET that turns
on fully with 3.1V of gate drive is needed. For designs of 5A
and under, dual MOSFETs in SO-8 provide a good trade-off
between size, cost, and efficiency.
CIN2 - A small (0.1 to 1 µF) ceramic capacitor should be
placed as close as possible to the drain of the high-side
MOSFET and source of the low-side MOSFET (dual MOS-
FETs make this easy). This capacitor should be X5R type
dielectric or better.
RCC, CCC- These are standard filter components designed to
ensure smooth DC voltage for the chip supply. RCC should
be 1 to 10Ω. CCC should 1 µF, X5R type or better.
CBOOT- Bootstrap capacitor, typically 100 nF.
RPULL-UP – This is a standard pull-up resistor for the open-
drain power good signal (PWGD). The recommended value
is 100 kΩ connected to VCC. If this feature is not necessary,
the resistor can be omitted.
D1 - A small Schottky diode should be used for the bootstrap.
It allows for a minimum drop for both high and low-side
drivers. The MBR0520 or BAT54 work well in most designs.
RCS - Resistor used to set the current limit. Since the design
calls for a peak current magnitude (IOUT + (0.5 x ∆IOUT)) of
4.8A, a safe setting would be 6A. (This is below the satura-
tion current of the output inductor, which is 7A.) Following the
equation from the Current Limit section, a 1.3 kΩ resistor
should be used.
RFADJ - This resistor is used to set the switching frequency of
the chip. The resistor value is approximated from the Fre-
quency vs Frequency Adjust Resistor curve in the Typical
Performance Characteristics section. For 300 kHz operation,
a 100 kΩ resistor should be used.
CSS - The soft-start capacitor depends on the user require-
ments and is calculated based on the equation given in the
section titled START UP/SOFT-START. Therefore, for a 7 ms
delay, a 12 nF capacitor is suitable.
Control Loop Compensation
The LM2745/8 uses voltage-mode (‘VM’) PWM control to
correct changes in output voltage due to line and load tran-
sients. VM requires careful small signal compensation of the
control loop for achieving high bandwidth and good phase
The control loop is comprised of two parts. The first is the
power stage, which consists of the duty cycle modulator,
output inductor, output capacitor, and load. The second part
is the error amplifier, which for the LM2745/8 is a 9 MHz
op-amp used in the classic inverting configuration. Figure 13
shows the regulator and control loop components.