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LM10011 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
LM10011 6/4-Bit VID Programmable Current DAC for Point of Load Regulators with Adjustable Start-Up Current TI
Texas Instruments TI
LM10011 Datasheet PDF : 24 Pages
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LM10011
SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014
www.ti.com
6.2 Handling Ratings
MIN
Tstg
Storage temperature range
–65
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
MAX
150
2
1
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
°C
kV
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
IDAC_OUT
VIDA, VIDB, VIDC, VIDS, EN, MODE
Junction Temperature
Ambient Temperature
MIN
MAX
2.97
5.5
–0.3 VDD – 1.75
–0.3
5.5
40
125
40
125
UNIT
V
V
V
°C
°C
6.4 Thermal Information
THERMAL METRIC(1)
LM10011
DSC
UNIT
RθJA
RθJC(top)
RθJB
ψJT
ψJB
RθJC(bot)
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
10 PINS
52.1
30.6
26.8
0.9
26.9
7.7
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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