LIS331HH
Register description
Table 25.
LIR2
I2_CFG1,
I2_CFG0
LIR1
I1_CFG1,
I1_CFG0
CTRL_REG3 description (continued)
Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by
reading INT2_SRC itself. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
Data signal on INT 2 pad control bits. Default value: 00.
(see table below)
Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by
reading INT1_SRC register. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
Data signal on INT 1 pad control bits. Default value: 00.
(see table below)
7.4
Table 26. Data signal on INT 1 and INT 2 pad
I1(2)_CFG1
I1(2)_CFG0
INT 1(2) Pad
0
0
Interrupt 1 (2) source
0
1
Interrupt 1 source OR interrupt 2 source
1
0
Data ready
1
1
Boot running
CTRL_REG4 (23h)
Table 27. CTRL_REG4 register
BDU
BLE
FS1
FS0
STsign
0
ST
SIM
Table 28.
BDU
BLE
FS1, FS0
STsign
ST
SIM
CTRL_REG4 description
Block data update. Default value: 0
(0: continuos update; 1: output registers not updated between MSB and LSB reading)
Big/little endian data selection. Default value 0.
(0: data LSB @ lower address; 1: data MSB @ lower address)
Full-scale selection. Default value: 00.
(00: ±6 g; 01: ±12 g; 11: ±24 g)
Self-test sign. Default value: 00.
(0: self-test plus; 1 self-test minus)
Self-test enable. Default value: 0.
(0: self-test disabled; 1: self-test enabled)
SPI serial interface mode selection. Default value: 0.
(0: 4-wire interface; 1: 3-wire interface)
Doc ID 16366 Rev 1
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