Register description
7
Register description
LIS331HH
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration data. The registers address, made of 7 bits, is used to identify them and to
write the data through serial interface.
7.1
CTRL_REG1 (20h)
Table 16. CTRL_REG1 register
PM2
PM1
PM0
DR1
DR0
Zen
Yen
Xen
Table 17. CTRL_REG1 description
PM2 - PM0
Power mode selection. Default value: 000
(000: Power-down; Others: refer to Table 18)
DR1, DR0
Data rate selection. Default value: 00
(00:50 Hz; Others: refer to Table 19)
Z axis enable. Default value: 1
Zen
(0: Z axis disabled; 1: Z axis enabled)
Y axis enable. Default value: 1
Yen
(0: Y axis disabled; 1: Y axis enabled)
X axis enable. Default value: 1
Xen
(0: X axis disabled; 1: X axis enabled)
PM bits allow to select between power-down and two operating active modes. The device is
in power-down mode when PD bits are set to “000” (default value after boot). Table 18
shows all the possible power mode configurations and respective output data rates. Output
data in the low-power modes are computed with low-pass filter cut-off frequency defined by
DR1, DR0 bits.
DR bits, in the normal-mode operation, select the data rate at which acceleration samples
are produced. In low-power mode they define the output data resolution. Table 19 shows all
the possible configuration for DR1 and DR0 bits.
Table 18.
PM2
0
0
0
0
1
Power mode and low-power output data rate configurations
PM1
PM0
Power mode selection
Output data rate [Hz]
ODRLP
0
0
Power-down
--
0
1
Normal mode
ODR
1
0
Low-power
0.5
1
1
Low-power
1
0
0
Low-power
2
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Doc ID 16366 Rev 1