LIS331HHTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
LIS331HHTR
STMicroelectronics
LIS331HHTR Datasheet PDF : 37 Pages
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Digital interfaces
LIS331HH
5.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS331HH is 001100xb. SDO/SA0 pad can be
used to modify less significant bit of the device address. If SA0 pad is connected to voltage
supply, LSb is ‘1’ (address 0011001b) else if SA0 pad is connected to ground, LSb value is
‘0’ (address 0011000b). This solution permits to connect and address two different
accelerometers to the same I2C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LIS331HH behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSB enables address auto increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the Master will transmit to the slave with direction unchanged. Table 10 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 10. SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SA0
Read
001100
0
Write
001100
0
Read
001100
1
Write
001100
1
R/W
SAD+R/W
1
00110001 (31h)
0
00110000 (30h)
1
00110011 (33h)
0
00110010 (32h)
Table 11.
Master
Slave
Transfer when master is writing one byte to slave
ST
SAD + W
SUB
DATA
SAK
SAK
SP
SAK
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Doc ID 16366 Rev 1
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