LB11693
Allowable Operating Conditions at Ta = 25°C
Parameter
Supply voltage range
Constant voltage output current
RD output current
FG output current
Symbol
VCC
IREG
IRD
IFG
Conditions
Ratings
Unit
9.5 to 28
V
0 to –30
mA
0 to 10
mA
0 to 10
mA
Electrical Characteristics at Ta = 25°C, VCC = VM = 24 V
Parameter
Current drain 1
Current drain 2
Output Block
Output saturation voltage 1
Output saturation voltage 2
Output leakage current
High side diode forward voltage 1
High side diode forward voltage 2
5 V Constant Voltage Output
Output voltage
Line regulation
Load regulation
Hall Sensor Amplifier
Input bias current
Differential-mode input voltage range
Common-mode input voltage range
Input offset voltage
CSD Pin
High-level output voltage
Low-level output voltage
External capacitor charge current
External capacitor discharge current
Charge/discharge current ratio
Undervoltage Protection Circuit (LVS pin)
Operating voltage
Release voltage
Hysteresis
Current Limiter Circuit (RF pin)
Limit voltage
Thermal Protection Operation
Thermal protection operating temperature
Hysteresis
CTL Amplifier
Input offset voltage
Input bias current
Common-mode input voltage range
High-level output voltage
Low-level output voltage
Open-loop gain
PWM Oscillator Circuit
High-level output voltage
Low-level output voltage
Amplitude
External capacitor charge current
Oscillator frequency
TOC Pin
Input voltage 1
Input voltage 2
Input voltage 1L
Input voltage 2L
Input voltage 1H
Input voltage 2H
Symbol
ICC1
ICC2
Stop mode
Conditions
VOsat1
VOsat2
IOleak
VD1
VD2
IO = 0.7 A, VO (SINK) + VO (SOURCE)
IO = 1.5 A, VO (SINK) + VO (SOURCE)
ID = 0.7 A
ID = 1.5 A
Ratings
min
typ
max
10
13.5
4.0
5.5
1.5
2.05
2.2
2.9
100
1.25
1.65
1.9
2.5
VREG
∆VREG1
∆VREG2
IO = –5 mA
VCC = 9.5 to 28 V
IO = –5 to –20 mA
IB (HA)
VHIN
VICM
VIOH
Sine wave input
Differential input, 50 mVp-p
Design target value
4.7
5.0
5.3
30
100
20
100
2
10
50
350
1.5
VREG – 1.0
–20
20
VOH (CSD)
VOL (CSD)
ICSD1
ICSD2
RCSD
Charge current/discharge current
2.75
3.0
3.25
0.85
1.0
1.15
–3.3
–2.4
–1.4
0.09
0.17
0.23
14
VSDL
VSDH
∆VSD
3.6
3.8
4.0
4.1
4.3
4.5
0.35
0.5
0.65
VRF
VCC – VM
TSD
∆TSD
Design target value (junction temperature)
Design target value (junction temperature)
0.45
0.5
0.55
150
170
40
VIO (CTL)
IB (CTL)
VICM
VOH (CTL)
VOL (CTL)
G (CTL)
ITOC = –0.2 mA
ITOC = 0.2 mA
f (CTL) = 1 kHz
–10
+10
–1
+1
0
VREG – 1.7
VREG – 1.2 VREG – 0.8
0.8
1.05
45
51
VOH (PWM
VOL (PWM)
V (PWM)
ICHG VPWM = 2.1 V
f (PWM) C = 2200 pF
2.75
3.0
3.25
1.1
1.3
1.4
1.5
1.7
2.0
–125
–90
–70
15.5
19.5
27.0
VTOC1 Output duty: 100%
2.72
3.0
3.30
VTOC2 Output duty: 0%
1.07
1.3
1.45
VTOC1L Design target value, when VREG = 4.7 V, 100%
2.72
2.80
2.90
VTOC2L Design target value, when VREG = 4.7 V, 0%
1.07
1.17
1.27
VTOC1H Design target value, when VREG = 5.3 V, 100%
3.08
3.20
3.30
VTOC2H Design target value, when VREG = 5.3 V, 0%
1.21
1.33
1.45
Unit
mA
mA
V
V
µA
V
V
V
mV
mV
µA
mVp-p
V
mV
V
V
µA
µA
times
V
V
V
V
°C
°C
mV
µA
V
V
V
dB
V
V
Vp-p
µA
kHz
V
V
V
V
V
V
Continued on next page.
No.8095-2/12