MAX189AEWE(2012) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX189AEWE Datasheet PDF : 18 Pages
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MAX187/ MAX189
+5V, Low-Power, 12-Bit Serial ADCs
A. SPI
B. QSPI
I/O
SCK
MISO
+5V
SS
CS
SCK
MISO
+5V
SS
I/O
SK
SI
CS
SCLK
DOUT
MAX187
MAX189
CS
SCLK
DOUT
MAX187
MAX189
CS
SCLK
DOUT
MAX187
MAX189
C. MICROWIRE
Figure 13. Common Serial-Interface Connections to the
MAX187/MAX189
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the ADC,
QSPI allows the minimum number of clock cycles neces-
sary to clock in the data. The MAX187/MAX189 require
13 clock cycles from the FP to clock out the 12 bits of
data with no trailing 0s (Figure 15). The maximum clock
frequency to ensure compatibility with QSPI is 2.77MHz.
Opto-Isolated Interface,
Serial-to-Parallel Conversion
Many industrial applications require electrical isolation to
separate the control electronics from hazardous electri-
cal conditions, provide noise immunity, or prevent exces-
sive current flow where ground disparities exist between
the ADC and the rest of the system. Isolation amplifiers
typically used to accomplish these tasks are expensive.
In cases where the signal is eventually converted to a
digital form, it is cost effective to isolate the input using
opto-couplers in a serial link.
The MAX187 is ideal in this application because it includes
both T/H amplifier and voltage reference, operates from a
single supply, and consumes very little power (Figure 16).
The ADC results are transmitted across a 1500V isolation
barrier provided by three 6N136 opto-isolators. Isolated
power must be supplied to the converter and the isolated
side of the opto-couplers. 74HC595 three-state shift reg-
isters are used to construct a 12-bit parallel data output.
The timing sequence is identical to the timing shown
in Figure 8. Conversion speed is limited by the delay
through the opto-isolators. With a 140kHz clock, conver-
sion time is 100Fs.
The universal 12-bit parallel data output can also be used
without the isolation stage when a parallel interface is
required. Clock frequencies up to 2.9MHz are possible
without violating the 20ns shift-register setup time. Delay or
invert the clock signal to the shift registers beyond 2.9MHz.
1ST BYTE READ
SCLK
CS
HI-Z
tCONV
DOUT
MSB D10 D9 D8 D7 D6 D5
D4
EOC
Figure 14. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
Maxim Integrated
2ND BYTE READ
D3 D2 D1 LSB
HI-Z
14
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