MAX189AEWE(2012) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX189AEWE Datasheet PDF : 18 Pages
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MAX187/ MAX189
+5V, Low-Power, 12-Bit Serial ADCs
The effective resolution (effective number of bits) the
ADC provides can be determined by transposing the
above equation and substituting in the measured SINAD:
N = (SINAD - 1.76)/6.02. Figure 12 shows the effective
number of bits as a function of the input frequency for the
MAX187/MAX189.
Total Harmonic Distortion
If a pure sine wave is sampled by an ADC at greater than
the Nyquist frequency, the nonlinearities in the ADC’s
transfer function create harmonics of the input frequency
present in the sampled output data.
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not including
the DC component) to the RMS amplitude of the funda-
mental frequency. This is expressed as follows:
THD = 20log V2 2 + V3 2 + V4 2 + … VN2
V1
where V1 is the fundamental RMS amplitude, and V2
through VN are the amplitudes of the 2nd through
Nth harmonics. The THD specification in the Electrical
Characteristics includes the 2nd through 5th harmonics.
12.2
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
1
(UNDERSAMPLED)
10
100
1000
INPUT FREQUENCY (kHz)
Figure 12. Effective Bits vs. Input Frequency
Maxim Integrated
Applications Information
Connection to Standard Interfaces
The MAX187/MAX189 serial interface is fully compatible
with SPI, QSPI, and MICROWIRE standard serial inter-
faces.
If a serial interface is available, set the CPU’s serial inter-
face in master mode so the CPU generates the serial
clock. Choose a clock frequency up to 2.5MHz.
1) Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2) Wait the for the maximum conversion time specified
before activating SCLK. Alternatively, look for a DOUT
rising edge to determine the end of conversion.
3) Activate SCLK for a minimum of 13 clock cycles.
The first falling clock edge will produce the MSB of
the DOUT conversion. DOUT output data transitions
on SCLK’s falling edge and is available in MSB-first
format. Observe the SCLK to DOUT valid timing char-
acteristic. Data can be clocked into the FP on SCLK’s
rising edge.
4) Pull CS high at or after the 13th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the LSB.
5) With CS = high, wait the minimum specified time, tCS,
before launching a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversions end, wait for the minimum acquisition
time, tACQ, before starting a new conversion.
Data can be output in 1-byte chunks or continuously, as
shown in Figure 8. The bytes will contain the result of the
conversion padded with one leading 1, and trailing 0s if
SCLK is still active with CS kept low.
SPI and MICROWIRE
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion in progress. Wait until DOUT
goes high or the maximum specified 8.5Fs conversion
time. Two consecutive 1-byte reads are required to get
the full 12 bits from the ADC. DOUT output data transi-
tions on SCLK’s falling edge and is clocked into the FP
on SCLK’s rising edge.
The first byte contains a leading 1 and 7 bits of conver-
sion result. The second byte contains the remaining 5
bits and 3 trailing 0s. See Figure 13 for connections and
Figure 14 for timing.
13
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