KM416L8031BT-GLY View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
KM416L8031BT-GLY Datasheet PDF : 53 Pages
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128Mb DDR SDRAM
List of figures
Figure 1 : 128Mb Package Pinout
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Figure 2 : Package dimension
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Figure 3 :State digram
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Figure 4 : Power up and initialization sequence
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Figure 5 : Mode register set
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Figure 6 : Mode register set sequence
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Figure 7 : Extend mode register set
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Figure 8 : Bank activation command cycle timing
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Figure 9 : Burst read operation timing
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Figure 10 : Burst write operation timing
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Figure 11 : Read interrupted by a read timing
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Figure 12 : Read interrupted by a write and burst stop timing
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Figure 13 : Read interrupted by a precharge timing
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Figure 14 : Write interrupted by a write timing
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Figure 15 : Write interrupted by a read and DM timing
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Figure 16 : Write interrupted by a precharge and DM timing
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Figure 17 : Burst stop timing
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Figure 18 : DM masking timing
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Figure 19 : Read with auto precharge timing
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Figure 20 : Write with auto precharge timing
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Figure 21 : Auto refresh timing
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Figure 22 : Self refresh timing
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Figure 23 : Power down entry and exit timing
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Figure 24 : Output Load Circuit (SSTL_2)
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Figure 25 : I / V characteristics for input/output buffers:
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pull-up(above) and pull-down(below)
Figure 26 : QFC timing on read operation
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Figure 27 : QFC timing on write operation with tDQSSmax
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Figure 28 : QFC timing on write operation with tDQSSmin
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Figure 29 : QFC timing example for interrupted writes operation
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-7-
REV. 1.0 November. 2. 2000
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