ISL6307 View Datasheet(PDF) - Intersil
Part Name
Description
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ISL6307 Datasheet PDF : 34 Pages
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ISL6307
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that spaces
between the components are minimized while creating the
PHASE plane. Place the Intersil MOSFET driver IC as close
as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical
driver input and output signals. If possible, duplicate the
same placement of these components for each phase.
Next, place the input and output capacitors. Position one
high-frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to
the upper MOSFET drains as dictated by the component
size and dimensions. Long distances between input
capacitors and MOSFET drains result in too much trace
inductance and a reduction in capacitor performance. Locate
the output capacitors between the inductors and the load,
while keeping them in close proximity to the microprocessor
socket.
The ISL6307 can be placed off to one side or centered
relative to the individual phase switching components.
Routing of sense lines and PWM signals will guide final
placement. Critical small signal components to place close
to the controller include the ISEN resistors, RT resistor,
feedback resistor, and compensation components.
Bypass capacitors for the ISL6307 and ISL66XX driver bias
supplies must be placed next to their respective pins. Trace
parasitic impedances will reduce their effectiveness.
Plane Allocation and Routing
Dedicate one solid layer, usually a middle layer, for a ground
plane. Make all critical component ground connections with
vias to this plane. Dedicate one additional layer for power
planes; breaking the plane up into smaller islands of
common voltage. Use the remaining layers for signal wiring.
Route phase planes of copper filled polygons on the top and
bottom once the switching component placement is set. Size
the trace width between the driver gate pins and the
MOSFET gates to carry 4A of current. When routing
components in the switching path, use short wide traces to
reduce the associated parasitic impedances.
33
FN9224.0
March 9, 2006
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