powered down to prevent static current drain if the NTC pin
rests at an intermediate level.
The GPAD/IO1 pin is similar to that of the NTC/IO0 except it is
an open train only output with no resistive pull-up. Therefore, if
the output is set to a logic 1, the internal pull-down is turned off
and the pin is three-stated. The input function is the same as
NOTE: If the IO0 and/or IO1 pins are being used for their analog
functions, their respective GPIO output and input functions must be
disabled. The GPIO function may be totally disabled by clearing the
appropriate GPIOctrl bit.
General Purpose A/D Input
The GPAD/IO1 pin can be used as a general purpose A/D input
as needed. The configuration is controlled in the GPAD A/D
control register similar to the VP A/D control register. This pin
should be connected to ground if not used.
The ISL6295 supports a 2-wire bidirectional bus and data
transmission protocol that is fully compatible with the industry-
standard SMBus V1.1 Packet Error Checking (PEC) CRC-8
error correction protocols based on the I2C™ interface. This
interface is used to read and write data from/to the on-chip
registers and EEPROM. The device responds to the same
SMBus slave address for access to all functions. The following
is a brief overview of the SMBus/I2C™ operational
implementation in the ISL6295. Please refer to the SMBus V1.1
specification for complete operational details of this industry
standard interface. This specification can be obtained at the
SMBus Implementer's Forum web site at www.smbus.org.
SMBus is a two-wire multi-master bus, meaning that more than
one device capable of controlling the bus can be connected to
it. A master device initiates a bus transfer and provides the
clock signals. A slave device can receive data provided by the
master or can in return provide data to the master.
Since more than one device may attempt to take control of the
bus as a master, SMBus provides an arbitration mechanism,
based on I2C™ and relying on the wired-AND connection of all
SMBus devices residing on the bus. If two or more masters try
to place information on the bus, the first to produce a "ONE"
when the other(s) produce a "ZERO" loses arbitration and has
to release the bus.
The clock signals during arbitration are a wired-AND
combination of all the clocks provided by SMBus masters. Bus
clock signals from a master can only be altered by clock
stretching or by other masters and only during a bus arbitration
situation. In addition to bus arbitration, SMBus implements the
I2C™ method of clock low extending in order to accommodate
devices of different speeds on the same bus.
SMBus version 1.1 can be implemented at any voltage
between 3V and 5V +10%. Devices can be powered by the bus
VDD or by their own power source (such as Smart Batteries)
and they will inter-operate flawlessly as long as they adhere to
the SMBus electrical specifications.
SMBus DATA TRANSFERS
A device that sends data onto the SMBus is defined as a
transmitter, and a device receiving data as a receiver. The
device that controls the message is called a "master". The
devices that are controlled by the master are "slaves". The
SMBus must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and generates
START and STOP conditions. The ISL6295 operates as a
slave on the two-wire bus. Connections to the bus are made via
the open drain I/O lines SDA and SCL.
SMBus operates according to the following bus protocol:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is high will be interpreted as control
The SMBus specification defines the following bus
Bus Not Busy Both data and clock lines remain HIGH.
A change in the state of the data line, from HIGH to
LOW, while the clock is HIGH, defines a START
A change in the state of the data line, from LOW to
HIGH, while the clock line is HIGH, defines a STOP
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The
data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse
per bit of data. Each data transfer is initiated with a
START condition and terminated with a STOP
condition. The number of data bytes transferred
between START and STOP conditions is not limited,
and is determined by the master device. The
information is transferred byte-wise and each
receiver acknowledges with a ninth bit.
Acknowledge Each receiving device, when addressed, is obliged
to generate an Acknowledge bit after the reception of
each byte. The master device must generate an
extra clock pulse which is associated with this
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
October 25, 2005