6269BCRZ View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

6269BCRZ

High-Performance Notebook PWM Controller with Audio-Frequency Clamp

Intersil 

ISL6269B

minimum PWM frequency to a level beyond human hearing

when the output load current becomes low enough.

With FCCM pulled low, the converter will automatically enter

DEM after the PHASE pin has detected positive voltage,

while the LG gate-driver pin is high, for eight consecutive

PWM pulses. The converter will return to CCM on the

following cycle after the PHASE pin detects negative

voltage, indicating that the body diode of the low-side

MOSFET is conducting positive inductor current.

Overcurrent and Short-Circuit Protection

The overcurrent protection (OCP) and short circuit protection

(SCP) setpoint is programmed with resistor RSEN that is

connected across the ISEN and PHASE pins. The PHASE

pin is connected to the drain terminal of the low-side

MOSFET.

The SCP setpoint is internally set to twice the OCP setpoint.

When an OCP or SCP fault is detected, the PGOOD pin will

pulldown to 30Ω and latch off the converter. The fault will

remain latched until the EN pin has been pulled below the

falling EN threshold voltage VENTHF or if VVCC has decayed

below the falling POR threshold voltage VVCC_THF.

The OCP circuit does not directly detect the DC load current

leaving the converter. The OCP circuit detects the peak of

positive-flowing output inductor current. The low-side

MOSFET drain current ID is assumed to be equal to the

positive output inductor current when the high-side MOSFET

is off. The inductor current develops a negative voltage

across the rDS(ON) of the low-side MOSFET that is

measured shortly after the LG gate-driver output goes high.

The ISEN pin sources the OCP sense current ISEN, through

the OCP programming resistor RSEN, forcing the ISEN pin to

zero volts with respect to the GND pin. The negative voltage

across the PHASE and GND pins is nulled by the voltage

dropped across RSEN as ISEN conducts through it. An OCP

fault occurs if ISEN rises above the OCP threshold current

IOC while attempting to null the negative voltage across the

PHASE and GND pins. ISEN must exceed IOC on all the

PWM pulses that occur within 20µs. If ISEN falls below IOC

on a PWM pulse before 20µs has elapsed, the timer will be

reset. An SCP fault will occur within 10µs when ISEN

exceeds twice IOC. The relationship between ID and ISEN is

written as:

ISEN • RSEN = ID • rDS(ON)

(EQ. 3)

The value of RSEN is then written as:

RSEN

=

-⎝⎛--I--F----L----+-----I----P--2------P-----⎠⎞----•---O-----C-----S----P----•---r--D----S----(--O-----N----)

IOC

(EQ. 4)

Where:

- RSEN (Ω) is the resistor used to program the

overcurrent setpoint

- ISEN is the current sense current that is sourced from

the ISEN pin

- IOC is the ISEN threshold current sourced from the ISEN

pin that will activate the OCP circuit

- IFL is the maximum continuous DC load current

- IPP is the inductor peak-to-peak ripple current

- OCSP is the desired overcurrent setpoint expressed as

a multiplier relative to IFL

Overvoltage Protection

When an OVP fault is detected, the PGOOD pin will pull

down to 60Ω and latch-off the converter. The OVP fault will

remain latched until VVCC has decayed below the falling

POR threshold voltage VVCC_THF.

The OVP fault detection circuit triggers after the voltage

across the FB and GND pins has increased above the rising

overvoltage threshold VOVR. Although the converter has

latched-off in response to an OVP fault, the LG gate-driver

output will retain the ability to toggle the low-side MOSFET

on and off, in response to the output voltage transversing the

VOVR and VOVF thresholds.

Undervoltage Protection

When a UVP fault is detected, the PGOOD pin will pull down

to 95Ω and latch-off the converter. The fault will remain

latched until the EN pin has been pulled below the falling EN

threshold voltage VENTHF or if VVCC has decayed below the

falling POR threshold voltage VVCC_THF. The UVP fault

detection circuit triggers after the voltage across the FB and

GND pins has fallen below the undervoltage threshold VUV.

Over-Temperature

When the temperature of the ISL6269B increases above the

rising threshold temperature TOTR, the IC will enter an OTP

state that suspends the PWM , forcing the LG and UG

gate-driver outputs low. The status of the PGOOD pin does

not change nor does the converter latch-off. The PWM

remains suspended until the IC temperature falls below the

hysteresis temperature TOTHYS at which time normal PWM

operation resumes. The OTP state can be reset if the EN pin

is pulled below the falling EN threshold voltage VENTHF or if

VVCC decays below the falling POR threshold voltage

VVCC_THF. All other protection circuits function normally

during OTP. It is likely that the IC will detect an UVP fault

because in the absence of PWM, the output voltage

immediately decays below the undervoltage threshold VUV;

the PGOOD pin will pulldown to 95Ω and latch-off the

converter. The UVP fault will remain latched until the EN pin

has been pulled below the falling EN threshold voltage

VENTHF or if VVCC has decayed below the falling POR

threshold voltage VVCC_THF.

9

FN6280.2

May 30, 2007

Share Link: