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6269BCRZ Просмотр технического описания (PDF) - Intersil

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6269BCRZ Datasheet PDF : 14 Pages
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PVCC (Pin 12)
The PVCC pin is the input voltage bias for the LG low-side
MOSFET gate driver. Connect +5V from the PVCC pin to the
PGND pin. Decouple with at least 1µF of an MLCC capacitor
across the PVCC and PGND pins.
BOOT (Pin 13)
The BOOT pin stores the input voltage for the UG high-side
MOSFET gate driver. Connect an MLCC capacitor across
the BOOT and PHASE pins. The boot capacitor is charged
through an internal boot diode connected from the PVCC pin
to the BOOT pin, each time the PHASE pin drops below
PVCC minus the voltage dropped across the internal boot
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VW is the higher threshold voltage. Figure 3 shows
PWM pulses being generated as VR traverses the VW and
VCOMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of VR; the PWM switching frequency is inversely
proportional to the voltage between VW and VCOMP.
Ripple Capacitor Voltage CR
Window Voltage VW
UG (Pin 14)
The UG pin is the output of the high-side MOSFET gate
driver. Connect to the gate of the high-side MOSFET.
Error Amplifier Voltage VCOMP
PHASE (Pin 15)
The PHASE pin detects the voltage polarity of the PHASE
node and is also the current return path for the UG high-side
MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor.
PGOOD (Pin 16)
The PGOOD pin is an open-drain output that indicates when
the converter is able to supply regulated voltage. Connect
the PGOOD pin to +5V through a pull-up resistor.
Theory of Operation
The ISL6269B is a hybrid of fixed frequency PWM control,
and variable frequency hysteretic control. Intersil’s R3
technology can simultaneously affect the PWM switching
frequency and PWM duty cycle in response to input voltage
and output load transients. The term “Ripple” in the name
“Robust-Ripple-Regulator” refers to the converter output
inductor ripple current, not the converter output ripple
voltage. The R3 modulator synthesizes an AC signal VR,
which is an ideal representation of the output inductor ripple
current. The duty-cycle of VR is the result of charge and
discharge current through a ripple capacitor CR. The current
through CR is provided by a transconductance amplifier gm
that measures the VIN and VO pin voltages. The positive
slope of VR can be written as:
(EQ. 1)
Power-On Reset
The ISL6269B is disabled until the voltage VVCC has
increased above the rising power-on reset (POR) VVCC_THR
threshold voltage. The controller will become once again
disabled when the voltage VVCC decreases below the falling
POR VVCC_THF threshold voltage.
EN, Soft-Start, and PGOOD
The ISL6269B uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the inrush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pin is pulled above
the rising EN threshold voltage VENTHR the PGOOD
Soft-Start Delay tSS begins and the output voltage begins to
rise. The output voltage enters regulation in approximately
1.5ms and the PGOOD pin goes to high impedance once tSS
has elapsed.
The negative slope of VR can be written as:
(EQ. 2)
Where gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
May 30, 2007
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