6269BCRZ View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
6269BCRZ Datasheet PDF : 14 Pages
| |||
ISL6269B
FCCM (Pin 3), EN (Pin 4), and PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
COMP (Pin 5), FB (Pin 6), and VO (Pin 8)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 7)
This pin requires a quiet environment. The resistor RFSET
and capacitor CFSET should be placed directly adjacent to
this pin. Keep fast moving nodes away from this pin.
ISEN (Pin 9)
Route the connection to the ISEN pin away from the traces
and components connected to the FB pin, COMP pin, and
FSET pin.
LG (Pin 11)
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
proximity with these traces on any layer.
BOOT (Pin 13), UG (Pin 14), and PHASE (Pin 15)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UG and PHASE pins in parallel with short
and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
13
FN6280.2
May 30, 2007
|
|
Share Link: 