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6269BIRZ Просмотр технического описания (PDF) - Intersil

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6269BIRZ High-Performance Notebook PWM Controller with Audio-Frequency Clamp Intersil
Intersil Intersil
6269BIRZ Datasheet PDF : 14 Pages
First Prev 11 12 13 14
ISL6269B
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as:
D
=
-V----O----U----T--
VIN
(EQ. 9)
The output inductor peak-to-peak ripple current is written as:
IPP
=
V-----O----U----T-------(---1-----–----D-----)
fSW LOUT
(EQ. 10)
A typical step-down DC/DC converter will have an IPP of
20% to 40% of the maximum DC output load current. The
value of IPP is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by:
PCOPPER
=
IL
O
A
2
D
D
C
R
(EQ. 11)
Where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance
COUT into which ripple current IPP can flow. Current IPP
develops a corresponding ripple voltage VPP across COUT,
which is the sum of the voltage drop across the capacitor
ESR and of the voltage change stemming from charge
moved in and out of the capacitor. These two voltages are
written as:
ΔVESR = IPP ESR
and
ΔVC
=
---------------I--P----P----------------
8 COUT fSW
(EQ. 12)
(EQ. 13)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required VPP is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors constructed with reverse package
geometry are available. A capacitor dissipates heat as a
function of RMS current and frequency. Be sure that IPP is
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at fSW.
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 7 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as:
(IM
A
2
X
(D
D2)
)
+
x
IMAX2
1--D--2--
IIN_RMS
=
----------------------------------------------------------------------------------------------------
IMAX
(EQ. 14)
Where:
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
D = -V----I-V-N---O----U-E----TF-----F--
(EQ. 15)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
x=1
x = 0.75
0.20
x = 0.50
x = 0.25
0.15
x=0
0.10
0.05
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
DUTY CYCLE
FIGURE 7. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
11
FN6280.2
May 30, 2007
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