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6269ACRZ Просмотр технического описания (PDF) - Intersil

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6269ACRZ High-Performance Notebook PWM Controller Intersil
Intersil Intersil
6269ACRZ Datasheet PDF : 13 Pages
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ISL6269A
exceeds twice IOC. The relationship between ID and ISEN is
written as:
ISEN RSEN = ID rDS(on)
(EQ. 3)
The value of RSEN is then written as:
RSEN
=
-⎝⎛--I--F----L----+-----I----P--2------P-----⎠⎞-------O-----C-----S----P-------r--D----S----(--o---n----)
IOC
(EQ. 4)
Where:
- RSEN () is the resistor used to program the
overcurrent setpoint
- ISEN is the current sense current that is sourced from
the ISEN pin
- IOC is the ISEN threshold current sourced from the ISEN
pin that will activate the OCP circuit
- IFL is the maximum continuous DC load current
- IPP is the inductor peak-to-peak ripple current
- OCSP is the desired overcurrent setpoint expressed as
a multiplier relative to IFL
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will pull
down to 60and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF.
The OVP fault detection circuit triggers after the voltage
across the FB and GND pins has increased above the rising
overvoltage threshold VOVR. Although the converter has
latched-off in response to an OVP fault, the LG gate-driver
output will retain the ability to toggle the low-side MOSFET
on and off, in response to the output voltage transversing the
VOVR and VOVF thresholds.
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down
to 95and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage VENTHF or if VCC has decayed below the
falling POR threshold voltage VVCC_THF. The UVP fault
detection circuit triggers after the voltage across the FB and
GND pins has fallen below the undervoltage threshold VUV.
Over-Temperature
When the temperature of the ISL6269A increases above the
rising threshold temperature TOTR, the IC will enter an OTP
state that suspends the PWM , forcing the LG and UG
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature TOTHYS at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage VENTHF or if
VCC decays below the falling POR threshold voltage
VVCC_THF. All other protection circuits function normally
during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage
immediately decays below the undervoltage threshold VUV;
the PGOOD pin will pulldown to 95and latch-off the
converter. The UVP fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
VENTHF or if VCC has decayed below the falling POR
threshold voltage VVCC_THF.
Programming the Output Voltage
When the converter is in regulation there will be 600mV from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 600mV with respect to the
GND pin when the converter is regulating at the desired
output voltage. The output voltage can be programmed from
600mV to 3.3V.
Programming the output voltage is written as:
VREF
=
V
O
U
T
------------R----B----O-----T---T----O----M---------------
RTOP + RBOTTOM
(EQ. 5)
Where:
- VOUT is the desired output voltage of the converter
- VREF is the voltage that the converter regulates to
between the FB pin and the GND pin
- RTOP is the voltage-programming resistor that connects
from the FB pin to the VO pin. In addition to setting the
output voltage, this resistor is part of the loop
compensation network
- RBOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Beginning with RTOP between 1kto 5kΩ, calculating
RBOTTOM is written as:
RBOTTOM
=
--V----R----E----F-------R----T----O-----P---
VOUT VREF
(EQ. 6)
Programming the PWM Switching Frequency
The ISL6269A does not use a clock signal to produce PWM.
The PWM switching frequency FSW is programmed by the
resistor RFSET that is connected from the FSET pin to the
GND pin. The approximate PWM switching frequency is
written as:
FSW
=
-------------1--------------
K RFSET
(EQ. 7)
Estimating the value of RFSET is written as:
RFSET
=
---------1----------
K FSW
(EQ. 8)
Where:
- FSW is the PWM switching frequency
- RFSET is the FSW programming resistor
- K =75 x 10-12
9
FN9253.1
August 7, 2006
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