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6269ACRZ Просмотр технического описания (PDF) - Intersil

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6269ACRZ High-Performance Notebook PWM Controller Intersil
Intersil Intersil
6269ACRZ Datasheet PDF : 13 Pages
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ISL6269A
MOSFET Gate-Drive Outputs LG and UG
The ISL6269A has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The LG gate-driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant, requiring a low
rDS(on) MOSFET. The LG pulldown resistance is small in
order to clamp the gate of the MOSFET below the VGS(th) at
turnoff. The current transient through the gate at turnoff can
be considerable because the switching charge of a low
rDS(on) MOSFET can be large. Adaptive shoot-through
protection prevents a gate-driver output from turning on until
the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 4. begins
only after the adaptive shoot-through protection has granted
permission for the driver to go high. The high-side gate-
driver output voltage is measured across the UG and
PHASE pins while the low-side gate-driver output voltage is
measured across the LG and PGND pins. The power for the
LG gate-driver is sourced directly from the PVCC pin. The
power for the UG gate-driver is sourced from a “boot”
capacitor connected across the BOOT and PHASE pins.
The boot capacitor is charged from a 5V bias supply through
a “boot diode” each time the low-side MOSFET turns on,
pulling the PHASE pin low. The ISL6269A has an integrated
boot diode connected from the PVCC pin to the BOOT pin.
tLGFUGR
tUGFLGR
UG
LG
FIGURE 4. LG AND UG DEAD-TIME
Diode Emulation
The ISL6269A can be configured to operate in continuous-
conduction-mode (CCM) or diode-emulation-mode (DEM),
which can improve light-load efficiency by allowing the
low-side MOSFET to block negative inductor current flow.
DEM is permitted when the FCCM pin is pulled low, and is
disabled when pulled high.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current flows into the
source of the high-side MOSFET, or the drain of the low-side
MOSFET. When the low-side MOSFET conducts positive
inductor current, the phase voltage will be negative with
respect to the GND pin. Conversely, when the low-side
MOSFET conducts negative inductor current, the phase
voltage will be positive with respect to the GND pin. Negative
inductor current occurs in CCM when the output load current
is less than ½ the inductor ripple current. Sinking negative
inductor through the low-side MOSFET lowers efficiency
through conduction losses. While in DEM the PWM
switching frequency is automatically shifted downward by an
increase of the window voltage VW. The PWM switching
frequency will continue to decrease as the load continues to
decrease. The reduction of PWM frequency further improves
efficiency by reducing switching losses. With FCCM pulled
low, the converter will automatically enter DEM after the
PHASE pin has detected positive voltage, while the LG
gate-driver pin is high, for eight consecutive PWM pulses.
The converter will return to CCM on the following cycle after
the PHASE pin detects negative voltage, indicating that the
body diode of the MOSFET is conducting positive inductor
current.
Overcurrent and Short-Circuit Protection
The overcurrent protection (OCP) and short circuit protection
(SCP) setpoint is programmed with resistor RSEN that is
connected across the ISEN and PHASE pins. The PHASE
pin is connected to the drain terminal of the low-side
MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint.
When an OCP or SCP fault is detected, the PGOOD pin will
pulldown to 30and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF.
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side
MOSFET drain current ID is assumed to be equal to the
positive output inductor current when the high-side MOSFET
is off. The inductor current develops a negative voltage
across the rDS(on) of the low-side MOSFET that is measured
shortly after the LG gate-driver output goes high. The ISEN
pin sources the OCP sense current ISEN, through the OCP
programming resistor RSEN, forcing the ISEN pin to zero
volts with respect to the GND pin. The negative voltage
across the PHASE and GND pins is nulled by the voltage
dropped across RSEN as ISEN conducts through it. An OCP
fault occurs if ISEN rises above the OCP threshold current
IOC while attempting to null the negative voltage across the
PHASE and GND pins. ISEN must exceed IOC on all the
PWM pulses that occur within 20µs. If ISEN falls below IOC
on a PWM pulse before 20µs has elapsed, the timer will be
reset. An SCP fault will occur within 10µs when ISEN
8
FN9253.1
August 7, 2006
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