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6269ACRZ Просмотр технического описания (PDF) - Intersil

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6269ACRZ High-Performance Notebook PWM Controller Intersil
Intersil Intersil
6269ACRZ Datasheet PDF : 13 Pages
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ISL6269A
Theory of Operation
Modulator
The ISL6269A is a hybrid of fixed frequency PWM control,
and variable frequency hysteretic control. Intersil’s R3
technology can simultaneously affect the PWM switching
frequency and PWM duty cycle in response to input voltage
and output load transients. The term “Ripple” in the name
“Robust-Ripple-Regulator” refers to the converter output
inductor ripple current, not the converter output ripple
voltage. The R3 modulator synthesizes an AC signal VR,
which is an ideal representation of the output inductor ripple
current. The duty-cycle of VR is the result of charge and
discharge current through a ripple capacitor CR. The current
through CR is provided by a transconductance amplifier gm
that measures the VIN and VO pin voltages. The positive
slope of VR can be written as:
VRPOS = (gm) (VIN VOUT)
(EQ. 1)
The negative slope of VR can be written as:
VRNEG = gm VOUT
(EQ. 2)
Where:
- gm is the gain of the transconductance amplifier
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VW is the higher threshold voltage. Figure 2 shows
PWM pulses being generated as VR traverses the VW and
VCOMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of VR; the PWM switching frequency is inversely
proportional to the voltage between VW and VCOMP.
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
PWM
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Power-On Reset
The ISL6269A is disabled until the voltage at the VCC pin
has increased above the rising power-on reset (POR) VCCR
threshold voltage. The controller will become once again
disabled when the voltage at the VCC pin decreases below
the falling POR VCCF threshold voltage.
EN, Soft-Start, and PGOOD
The ISL6269A uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the soft-
start sequence has been selected to limit the inrush current
through the output capacitors as they charge to the desired
regulation voltage. When the EN pin is pulled above the rising
EN threshold voltage VENTHR the PGOOD Soft-Start Delay
TSS begins and the output voltage begins to rise. The output
voltage enters regulation in approximately 1.5ms and the
PGOOD pin goes to high impedance once TSS has elapsed.
1.5ms
VOUT
VCC and PVCC
EN
PGOOD
2.75ms
FIGURE 3. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if VCC has not reached the rising POR
threshold VCCR, or if VCC is below the falling POR threshold
VCCF. The ISL6269A features a unique fault-identification
capability that can drastically reduce trouble-shooting time
and effort. The pull-down resistance of the PGOOD pin
corresponds to the fault status of the controller. During soft-
start or if an undervoltage fault occurs, the PGOOD pulldown
resistance is 95, or 30for an overcurrent fault, or 60for
an overvoltage fault.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
VCC Below POR
Undefined
Soft Start or Undervoltage
95
Overvoltage
60
Overcurrent
30
7
FN9253.1
August 7, 2006
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