ISL6269A
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors constructed with reverse package
geometry are available. A capacitor dissipates heat as a
function of RMS current and frequency. Be sure that IPP is
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at FSW.
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 6 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as:
(
IMAX2
⋅
(D
–
D2))
+
⎛
⎝
x
⋅
IMAX2
⋅1--D--2--
⎞
⎠
IIN_RMS
=
----------------------------------------------------------------------------------------------------
IMAX
(EQ. 14)
Where:
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
D = ------V----O----U-----T-------
VIN ⋅ EFF
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
x=1
x = 0.75
0.2
x = 0.50
0.15
x = 0.25
x=0
0.1
0.05
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
DUTY CYCLE
FIGURE 6. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
VIN-VOUT across it. The preferred low-side MOSFET
emphasizes low rDS(on) when fully saturated to minimize
conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
PCON_LS ≈ ILOAD2 ⋅ rDS(on)_LS • (1 – D)
(EQ. 15)
For the high-side MOSFET, (HS), its conduction loss is
written as:
PCON_HS
=
IL
O
A
2
D
•
rD
S
(
o
n
)
_
H
S
•
D
(EQ. 16)
For the high-side MOSFET, its switching loss is written as:
PSW_HS
=
-V----I--N----•---I--V----A----L---L---E----Y-----•--T----O-----N----•---F----S----W--- + V-----I--N----•---I--P----E----A----K----•---T----O----F----F----•---F---S----W----
2
2
(EQ. 17)
Where:
- IVALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- TON is the time required to drive the device into
saturation
- TOFF is the time required to drive the device into cutoff
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
CBOOT
=
---------Q-----g---------
∆VBOOT
(EQ. 18)
Where:
- Qg is the total gate charge required to turn on the
high-side MOSFET
- ∆VBOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
11
FN9253.1
August 7, 2006