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6269ACRZ Просмотр технического описания (PDF) - Intersil

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6269ACRZ High-Performance Notebook PWM Controller Intersil
Intersil Intersil
6269ACRZ Datasheet PDF : 13 Pages
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ISL6269A
It is recommended that whenever the control loop
compensation network is modified, FSW should be checked
for the correct frequency and if necessary, adjust RFSET.
Compensation Design
The LC output filter has a double pole at its resonant frequency
that causes the phase to abruptly roll downward. The R3
modulator used in the ISL6269A makes the LC output filter
resemble a first order system in which the closed loop stability
can be achieved with a Type II compensation network.
R2
C1
C2
COMP
- FB
EA
+
REF
FSET
R3 Modulator
VO
VIN
R1
RFSET
CFSET
VOUT
VIN
UG
PHASE
Gate Drivers
LG
GND
ISL6269A
QHIGH_SIDE
LOUT
DCR
QLOW_SIDE
COUT
CESR
FIGURE 5. COMPENSATION REFERENCE CIRCUIT
Your local Intersil representative can provide a PC-based
tool that can be used to calculate compensation network
component values and help simulate the loop frequency
response. The compensation network consists of the internal
10
error amplifier of the ISL6269A and the external components
R1, R2, C1, and C2 as well as the frequency setting
components RFSET, and CFSET, are identified in the
schematic Figure 5.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as:
D = -V----O----U----T--
VIN
(EQ. 9)
The output inductor peak-to-peak ripple current is written as:
IPP
=
V-----O----U----T-------(---1----–-----D-----)
FSW LOUT
(EQ. 10)
A typical step-down DC/DC converter will have an IPP of
20% to 40% of the maximum DC output load current. The
value of IPP is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by:
PCOPPER = ILOAD2 DCR
(EQ. 11)
Where:
- ILOAD is the converter output DC current
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance
COUT into which ripple current IPP can flow. Current IPP
develops a corresponding ripple voltage VPP across COUT,
which is the sum of the voltage drop across the capacitor
ESR and of the voltage change stemming from charge
moved in and out of the capacitor. These two voltages are
written as:
VESR = IPP ESR
(EQ. 12)
and
VC
=
----------------I--P----P-----------------
8 COUT FSW
(EQ. 13)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required VPP is achieved.
FN9253.1
August 7, 2006
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