6269CRZ View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

6269CRZ

High-Performance Notebook PWM Controller with Bias Regulator and Audio-Frequency Clamp

Intersil 

ISL6269

LDO

Voltage applied to the VIN pin with respect to the GND pin is

regulated to +5VDC by an internal low-dropout voltage

regulator (LDO). The output of the LDO is called VCC, which

is the bias voltage used by the IC internal circuitry. The LDO

output is routed to the VCC pin and requires a ceramic

capacitor connected to the GND pin to stabilize the LDO and

to decouple load transients.

When the EN pin rises above the VENR threshold, VCC will

turn on and rise to its regulation voltage. The LDO regulates

VCC by pulling up towards the voltage at the VIN pin; the

LDO has no pull-down capability.

POR and Soft-Start

The power-on reset (POR) circuit monitors VCC for the

VCCR (rising) and VCCF (falling) voltage thresholds. The

purpose of soft-start is to limit the inrush current through the

output capacitors when the converter first turns on.The PWM

soft-start sequence initializes once VCC rises above the

VCCR threshold, beginning from below the VCCF threshold.

The ISL6269 uses a digital soft-start circuit to ramp the

output voltage of the converter to the programmed regulation

setpoint in approximately 1.5ms. The converter regulates to

600mV at the FB pin with respect to the GND pin. During

soft-start a digitally derived voltage reference forces the

converter to regulate from 0V to 600mV at the FB pin.

When the EN pin is pulled below the VENF threshold, the

LDO stops regulating and PWM immediately stops,

regardless of the falling VCC voltage. The soft-start

sequence can be reinitialized and fault latches reset, once

VCC falls below the VCCF threshold.

MOSFET Gate-Drive Outputs

The ISL6269 incorporates a MOSFET driver that controls

both high-side and low-side N-Channel MOSFETS. The

drivers are optimized for low duty-cycle applications

prevalent with large step down voltages. At low duty-cycle,

the low-side MOSFET conducts for a much longer time in a

switching period than the high-side MOSFET, necessitating

lower rDS(ON) at the expense of larger parasitic capacitance.

The low-side gate driver is therefore sized much larger to

meet this application requirement. The larger sink current

capability enables the low-side gate driver to hold the gate-

source voltage of the MOSFET below its VGSTH as current

conducts through the drain-to-gate parasitic capacitance.

Both drivers incorporate adaptive shoot-through protection

to prevent high-side and low-side MOSFETS from

conducting simultaneously and shorting the input supply.

During turn-off of the low-side MOSFET, the LG to PGND

voltage is monitored until it reaches a 1V threshold, at which

time the UG driver is allowed to switch. During turn-off of the

high-side MOSFET, the UG to PHASE voltage is monitored

until it reaches a 1V threshold, at which time the LG driver is

allowed to switch.

The input power for the LG driver circuit is sourced directly

from the PVCC pin. The input power for the UG driver circuit

is sourced from a “boot” capacitor connected from the BOOT

pin to the PHASE pin. The same supply that is connected to

the PVCC pin is used to charge the boot capacitor via the

internal Schottky diode of the IC.

tLGFUGR

UG

LG

tUGFLGR

FIGURE 4. GATE DRIVE TIMING DIAGRAM

10

FN9177.1

August 7, 2006

Share Link: