Functional Pin Description
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The bias supply for the IC’s control circuitry. Connect this pin
to a +5V supply and decouple using a quality 0.1µF ceramic
Battery supply voltage. It is used for input voltage feed-forward
to improve the input line transient performance.
The power supply pin for the internal MOSFET gate drivers
of the ISL6265A. Connect this pin to a +5V power supply.
Decouple this pin with a quality 1.0µF ceramic capacitor.
The bias and reference ground for the IC. The GND
connection for the ISL6265A is through the thermal pad on
the bottom of the package.
A 117kΩ resistor from RBIAS to GND sets internal reference
currents. The addition of capacitance to this pin must be
avoided and can create instabilities in operation.
A resistor from this pin to GND programs a DC current
source, which generates a positive offset voltage across the
resistor between FB and VDIFF pins. In this case, the OFS
pin voltage is +1.2V and VFIX mode is not enabled. If OFS is
pulled up to +3.3V, VFIX mode is enabled, the DAC decodes
the SVC and SVD inputs to determine the programmed
voltage, and the OFS function is disabled. If OFS is pulled up
to +5V, the OFS function and VFIX mode are disabled.
System power good input. When this pin is high, the SVI
interface is active and I2C protocol is running. While this pin
is low, the SVC, SVD, and VFIXEN input states determine
the pre-PWROK metal VID or VFIX mode voltage. This pin
must be low prior to the ISL6265A PGOOD output going
high per the AMD SVI Controller Guidelines.
Controller power-good open-drain output. This pin is typically
pulled up externally by a 2.0kΩ resistor to +3.3V. During
normal operation, this pin indicates whether all output
voltages are within specified overvoltage and undervoltage
limits and no overcurrent condition is present. If any output
voltage exceeds these limits or a reset event occurs, the pin is
pulled low. This pin is always low prior to the end of soft-start.
This pin is the serial VID clock input from the AMD processor.
This pin is the serial VID data bidirectional signal to and from
the master device on the AMD processor.
Digital input enable. A high level logic signal on this pin
enables the ISL6265A.
A resistor from this pin to GND programs the switching
frequency of the Northbridge controller (for example,
22.1k ~ 260kHz).
This pin is the output voltage feedback to the inverting input
of the Northbridge controller error amplifier.
This pin is the output of the Northbridge controller error
Remote Northbridge voltage sense input and return.
Connect isolated traces from these pins to the Northbridge
sense points of the processor.
Overcurrent protection selection input for the Northbridge
controller. A resistor from this pin to PHASE_NB sets the OC
Upper MOSFET gate signal from Northbridge controller.
Lower MOSFET gate signal from Northbridge controller.
May 11, 2009