6265AHRTZ View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

6265AHRTZ

Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

Intersil 

ISL6265A

Functional Pin Description

48 47 46 45 44 43 42 41 40 39 38 37

OFS/VFIXEN 1

PGOOD 2

PWROK 3

SVD 4

SVC 5

ENABLE 6

RBIAS 7

OCSET 8

VDIFF0 9

FB0 10

COMP0 11

VW0 12

49

GND

[BOTTOM]

36 BOOT_NB

35 BOOT0

34 UGATE0

33 PHASE0

32 PGND0

31 LGATE0

30 PVCC

29 LGATE1

28 PGND1

27 PHASE1

26 UGATE1

25 BOOT1

13 14 15 16 17 18 19 20 21 22 23 24

VCC

The bias supply for the IC’s control circuitry. Connect this pin

to a +5V supply and decouple using a quality 0.1µF ceramic

capacitor.

VIN

Battery supply voltage. It is used for input voltage feed-forward

to improve the input line transient performance.

PVCC

The power supply pin for the internal MOSFET gate drivers

of the ISL6265A. Connect this pin to a +5V power supply.

Decouple this pin with a quality 1.0µF ceramic capacitor.

GND

The bias and reference ground for the IC. The GND

connection for the ISL6265A is through the thermal pad on

the bottom of the package.

RBIAS

A 117kΩ resistor from RBIAS to GND sets internal reference

currents. The addition of capacitance to this pin must be

avoided and can create instabilities in operation.

OFS/VFIXEN

A resistor from this pin to GND programs a DC current

source, which generates a positive offset voltage across the

resistor between FB and VDIFF pins. In this case, the OFS

pin voltage is +1.2V and VFIX mode is not enabled. If OFS is

pulled up to +3.3V, VFIX mode is enabled, the DAC decodes

the SVC and SVD inputs to determine the programmed

voltage, and the OFS function is disabled. If OFS is pulled up

to +5V, the OFS function and VFIX mode are disabled.

PWROK

System power good input. When this pin is high, the SVI

interface is active and I2C protocol is running. While this pin

is low, the SVC, SVD, and VFIXEN input states determine

the pre-PWROK metal VID or VFIX mode voltage. This pin

must be low prior to the ISL6265A PGOOD output going

high per the AMD SVI Controller Guidelines.

PGOOD

Controller power-good open-drain output. This pin is typically

pulled up externally by a 2.0kΩ resistor to +3.3V. During

normal operation, this pin indicates whether all output

voltages are within specified overvoltage and undervoltage

limits and no overcurrent condition is present. If any output

voltage exceeds these limits or a reset event occurs, the pin is

pulled low. This pin is always low prior to the end of soft-start.

SVC

This pin is the serial VID clock input from the AMD processor.

SVD

This pin is the serial VID data bidirectional signal to and from

the master device on the AMD processor.

ENABLE

Digital input enable. A high level logic signal on this pin

enables the ISL6265A.

FSET_NB

A resistor from this pin to GND programs the switching

frequency of the Northbridge controller (for example,

22.1k ~ 260kHz).

FB_NB

This pin is the output voltage feedback to the inverting input

of the Northbridge controller error amplifier.

COMP_NB

This pin is the output of the Northbridge controller error

amplifier.

VSEN_NB, RTN_NB

Remote Northbridge voltage sense input and return.

Connect isolated traces from these pins to the Northbridge

sense points of the processor.

OCSET_NB

Overcurrent protection selection input for the Northbridge

controller. A resistor from this pin to PHASE_NB sets the OC

trip point.

UGATE_NB

Upper MOSFET gate signal from Northbridge controller.

LGATE_NB

Lower MOSFET gate signal from Northbridge controller.

9

FN6884.0

May 11, 2009

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