The sense capacitor voltage, VC, will increase as inductor
current rises per Equation 7. When the inductor current rises
to the OC trip level, the voltage across the sense capacitor
will reach a maximum based on the resistor ratio K. This
maximum value, VC(OC), is gained up by a factor of 5 and
compared to the static OC trip level set by the OCSET pin.
The recommended voltage range for VC,OC is 6mV to 25mV,
which sets the resistor divider ratio K, where IOC is the
user-defined OC trip level (see Equation 13). Typical
inductor DCR values are on the order of 1mΩ which result in
more than enough voltage drop to support this VC,OC range.
IOC ⋅ DCR
The resistor divider components also impact time-constant
matching, these components need to meet the parallel
combination requirements of Equation 9.
Based on the selected VC(OC) level, the required OC monitor
trip level is set. The recommended VC(OC) level range will
result in an OC monitor trip level range of 30mV to 125mV
based on the internal gain of 5.
This OC monitor trip level sets the voltage level required at
the OCSET pin to create an OC fault at the user-defined OC
trip level. A resistor divider from the RBIAS pin to ground
with the mid-point connected to OCSET sets the voltage at
the pin (see Figure 10). This voltage is internally divided by 6
and compared with VC(OC). Working backwards, the voltage
required at the OCSET pin to achieve this OC trip level
ranges from 180mV to 0.750mV as defined in Equation 14.
VOCSET = VC(OC) ⋅ 30
The resistor divider ratio used to determine the RBIAS and
ROCSET values is shown in Equation 15.
ROCSET + RBIAS
The resistor values must also meet the RBIAS requirement
that the total series resistance to ground equal 117kΩ. An
OC condition must be sustained for 100µs before action is
taken by the controller in response to the OC fault.
A short-circuit OC loop is also active based on the same
sense elements outlined above with a threshold set to 2.25
times the OCSET threshold set. The controller takes
immediate action when this fast OC fault is detected.
NORTHBRIDGE OC DETECTION
Northbridge OC sensing is achieved via rDS(ON) sensing
across the lower MOSFET. An internal 10µA current source
develops a voltage across ROCSET_NB, which is compared
with the voltage developed across the low-side MOSFET as
measured at the PHASE pin. When the voltage drop across
the MOSFET exceeds the voltage drop across the resistor,
an OC event occurs. The OCSET_NB resistor is selected
based on the relationship in Equation 16.
ROCSETNB = -I-O-----C-----1⋅---0r--D--μ---S-A---(--O----N----)
Where IOC is the OC trip level selected for the Northbridge
application and rDS(ON) is the drain-source ON-resistance of
the lower MOSFET.
OC FAULT RESPONSE
When an OC fault occurs on any combination of outputs,
both Core and Northbridge regulators shutdown and the
driver outputs are tri-stated. The PGOOD signal transitions
low indicating a fault condition. The controller will not attempt
to restart the regulators and the user must toggle either EN
or VCC to clear the fault condition.
The ISL6265A monitors the individual Core and Northbridge
output voltages using differential remote sense amplifiers.
The ISL6265A features a severe overvoltage (OV) threshold
of 1.8V. If any of the outputs exceed this voltage, an OV fault
is immediately triggered. PGOOD is latched low and the
low-side MOSFETs of the offending output(s) are turned on.
The low-side MOSFETs will remain on until the output
voltage is pulled below 0.85V at which time all MOSFETs are
turned off. If the output again rises above 1.8V, the
protection process repeats. This offers protection against a
shorted high-side MOSFET while preventing output voltage
from ringing below ground. The OV is reset by toggling EN
low. OV detection is active at all times that the controller is
enabled including after one of the other faults occurs so that
the processor is protected against high-side MOSFET
leakage while the MOSFETs are commanded off.
Undervoltage protection is independent of the OC limit. A
fault latches if any of the sensed output voltages are less
than the VID set value by a nominal 295mV for 205µs. The
PWM outputs turn off both Core and Northbridge internal
drivers and PGOOD goes low.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
Selecting the LC Output Filter
The output inductor and output capacitor bank form a
low-pass filter responsible for smoothing the pulsating
voltage at the phase node. The output filter also must
support the transient energy required by the load until the
controller can respond. Because it has a low bandwidth
May 11, 2009