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6265AHRTZ Просмотр технического описания (PDF) - Intersil

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6265AHRTZ Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs Intersil
Intersil Intersil
6265AHRTZ Datasheet PDF : 23 Pages
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ISL6265A
Efficiency can be further improved with a reduction of
unnecessary switching losses by reducing the PWM
frequency. It is characteristic of the R3 architecture for the
PWM frequency to decrease while in diode emulation. The
extent of the frequency reduction is proportional to the
reduction of load current. Upon entering DCM, the PWM
frequency makes an initial step-reduction because of a 33%
step-increase of the window voltage VW.
Power-Savings Mode
The ISL6265A has two operating modes to optimize
efficiency based on the state of the PSI_L input from the
AMD SVI control signal. When this input is low, the controller
expects to deliver low power and enters a power-savings
mode to improve efficiency in this low power state. The
controller’s operational modes are designed to work in
conjunction with the AMD SVI control signal to maintain the
optimal system configuration for all conditions.
Northbridge And Dual Plane Core
While PSI_L is high, the controller operates all three
regulators in forced CCM. If PSI_L is asserted low by the SVI
interface, the ISL6265A initiates DE in all three regulators.
This transition allows the controller to achieve the highest
possible efficiency over the entire load range for each output.
A smooth transition is facilitated by the R3 technology, which
correctly maintains the internally synthesized ripple current
throughout mode transitions of each regulator.
Uniplane Core
In uniplane mode, the ISL6265A Core regulator is in 2-phase
multiphase mode. The controller operates with both phases
fully active, responding rapidly to transients and delivering the
maximum power to the load. When the processor asserts
PSI_L low under reduced load levels, the ISL6265A sheds one
phase to eliminate switching losses associated with the idle
channel. Even with the regulator operating in single-phase
mode, transient response capability is maintained.
While operating in single-phase DE with PSI_L low, the lower
MOSFET driver switches the lower MOSFET off at the point of
zero inductor current to prevent discharge current from
flowing from the output capacitor bank through the inductor. In
DCM, switching frequency is proportionately reduced, thus
greatly reducing both conduction and switching loss. In DCM,
the switching frequency is defined by Equation 12.
FDCM
=
F----C-----C----M----2--
1.332
---------2-------L--------I--O-----------
VO
1
V-V----I-O-N--⎠⎟⎞
(EQ. 12)
Where FCCM is equivalent to the Core frequency set by
Equation 3.
Fault Monitoring and Protection
The ISL6265A actively monitors Core and Northbridge
output voltages and currents to detect fault conditions.
These fault monitors trigger protective measures to prevent
damage to the processor. One common power good
indicator is provided for linking to external system monitors.
Power-Good Signal
The power-good pin (PGOOD) is an open-drain logic output
that signals if the ISL6265A is not regulating Core and
Northbridge output voltages within the proper levels or
output current in one or more outputs has exceeded the
maximum current setpoint.
This pin must be tied to a +3.3V or +5V source through a
resistor. During shutdown and soft-start, PGOOD is pulled low
and is released high only after a successful soft-start has raised
Core and Northbridge output voltages within operating limits.
PGOOD is pulled low when an overvoltage, undervoltage, or
overcurrent (OC) condition is detected on any output or when
the controller is disabled by a POR or forcing enable (EN) low.
Once a fault condition is triggered, the controller acts to protect
the processor. The controller latches off and PGOOD is pulled
low. Toggling EN or VCC initiates a soft-start of all outputs. In
the event of an OV, the controller will not initiate a soft-start by
toggling EN, but requires VCC be lowered below the falling
POR threshold to reset.
Overcurrent Protection
Core and Northbridge outputs feature two different methods
of current sensing. Core output current sensing is achieved
via inductor DCR or discrete resistor sensing. The
Northbridge controller uses lower MOSFET rDS(ON) sensing
to detect output current.
CORE OC DETECTION
Core outputs feature an OC monitor which compares a
voltage set at the OCSET pin to the voltage measured
across the current sense capacitor, VC. When the voltage
across the current sense capacitor exceeds the programmed
trip level, the comparator signals an OC fault. Figure 10
shows the basic OC functions within the IC.
CURRENT
SENSE
SEE FIGURE 9 FOR
ADDITIONAL DETAIL
ISP
+
5x
ISN
V_c
5 x VC(OC) @
OC TRIP CURRENT
BIAS
CKT
OC
-
+
6
VOCSET
6
RBIAS 1.17V
10µA
OCSET
RBIAS
VOCSET
ROCSET
ISL6265A
FIGURE 10. OC TRIP CIRCUITRY
18
FN6884.0
May 11, 2009
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