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6265AHRTZ Просмотр технического описания (PDF) - Intersil

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6265AHRTZ Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs Intersil
Intersil Intersil
6265AHRTZ Datasheet PDF : 23 Pages
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ISL6265A
NORTHBRIDGE CURRENT SENSE
During the off-time following a PHASE transition low, the
Northbridge controller samples the voltage across the lower
MOSFET rDS(ON). A ground-referenced amplifier is
connected to the PHASE node through a resistor,
ROCSET_NB. The voltage across ROCSET_NB is equal to the
voltage drop across the rDS(ON) of the lower MOSFET while
it is conducting. The resulting current into the OCSET_NB
pin is proportional to the inductor current. The sensed
inductor current is used for overcurrent protection and
described in the “Fault Monitoring and Protection” on
page 18. The Northbridge controller does not support output
voltage droop.
Selecting RBIAS For Core Outputs
To properly bias the ISL6265A, a reference current is
established by placing a 117kΩ, 1% tolerance resistor from the
RBIAS pin to ground. This will provide a highly accurate, 10µA
current source from which OC reference current is derived.
Care must be taken in layout to place the resistor very close
to the RBIAS pin. A good quality signal ground should be
connected to the opposite end of the RBIAS resistor. Do not
connect any other components to this pin as this would
negatively impact performance. Capacitance on this pin
could create instabilities and is to be avoided.
A resistor divider off this pin is used to set the Core side OC
trip level. Additional direction on how to size is provided in
“Fault Monitoring and Protection” on page 18 on how to size
the resistor divider.
Offset Resistor Selection
If the OFS pin is connected to ground through a resistor, the
ISL6265A operates in SVI mode with droop active. The
resistor between the OFS pin and ground sets the positive
Core voltage offset per Equation 11.
ROFS
=
1----.--2---V---------R----F----B--
VOFS
(EQ. 11)
Where VOFS is the user defined output voltage offset.
Typically, VOFS is determined by taking half the total output
voltage droop. The resulting value centers the overall output
voltage waveform around the programmed SVID level. For
example, RFB of 1kΩ and a total output droop of 24mV would
result in an offset voltage of 12mV and a ROFS of 100kΩ.
Internal Driver Operation
The ISL6265A features three internal gate-drivers to support
the Core and Northbridge regulators and to reduce solution
size. The drivers include a diode emulation mode, which
helps to improve light-load efficiency.
MOSFET Gate-Drive Outputs
The ISL6265A has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The low-side gate-drivers
are optimized for low duty-cycle applications where the
low-side MOSFET conduction losses are dominant,
requiring a low rDS(ON) MOSFET. The LGATE pull-down
resistance is low in order to strongly clamp the gate of the
MOSFET below the VGS(th) at turn-off. The current transient
through the gate at turn-off can be considerable because the
gate charge of a low rDS(ON) MOSFET can be large.
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driver output
has fallen below approximately 1V.
The high-side gate-driver output voltage is measured across
the UGATE and PHASE pins while the low-side gate-driver
output voltage is measured across the LGATE and PGND
pins. The power for the LGATE gate driver is sourced
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a “boot” capacitor connected
across the BOOT and PHASE pins. The boot capacitor is
charged from a 5V bias supply through a “boot diode” each
time the low-side MOSFET turns on, pulling the PHASE pin
low. The ISL6265A has an integrated boot diode connected
from the PVCC pin to the BOOT pin.
Diode Emulation
The ISL6265A implements forced
continuous-conduction-mode (CCM) at heavy load and
diode-emulation-mode (DE) at light load, to optimize
efficiency in the entire load range. The transition is
automatically achieved by detecting the inductor current
when PSI_L is low. If PSI_L is high, the controller disables
DE and forces CCM on both Core and NB regulators.
Positive-going inductor current flows either from the source
of the high-side MOSFET, or into the drain of the low-side
MOSFET. Negative-going inductor current flows into the
drain of the low-side MOSFET. When the low-side MOSFET
conducts positive inductor current, the phase voltage is
negative with respect to the GND and PGND pins.
Conversely, when the low-side MOSFET conducts negative
inductor current, the phase voltage is positive with respect to
the GND and PGND pins. The ISL6265A monitors the phase
voltage when the low-side MOSFET is conducting inductor
current to determine the direction of the inductor current.
When the output load current is less than half the inductor
ripple current, the inductor current goes negative. Sinking the
negative inductor through the low-side MOSFET lowers
efficiency by preventing DCM period stretching and allowing
unnecessary conduction losses. In DE, the ISL6265A Core
regulators automatically enter DCM after the PHASE pin has
detected positive voltage and LGATE was allowed to go high.
The NB regulator enters DCM after the PHASE pin has
detected positive voltage and LGATE was allowed to go high
for eight consecutive PWM switching cycles. The ISL6265A
turns off the low-side MOSFET once the phase voltage turns
positive, indicating negative inductor current. The ISL6265A
returns to CCM on the following cycle after the PHASE pin
detects negative voltage, indicating that the body diode of the
low-side MOSFET is conducting positive inductor current.
17
FN6884.0
May 11, 2009
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