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6265AHRTZ Просмотр технического описания (PDF) - Intersil

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6265AHRTZ Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs Intersil
Intersil Intersil
6265AHRTZ Datasheet PDF : 23 Pages
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ISL6265A
It is recommended that whenever the control loop
compensation network is modified, the switching frequency
should be checked and adjusted by changing RFSET_NB if
necessary.
Current Sense
Core and Northbridge regulators feature two different types
of current sense circuits.
CORE CONTINUOUS CURRENT SENSE
The ISL6265A provides for load current to be measured
using either resistors in series with the individual output
inductors or using the intrinsic series resistance of the
inductors as shown in the applications circuits in Figures 2
and 3. The load current in a particular output is sampled
continuously every switching cycle. During this time, the
current-sense amplifier uses the current sense inputs to
reproduce a signal proportional to the inductor current. This
sensed current is a scaled version of the inductor current.
VIN
UGATE
MOSFET
DRIVER
LGATE
ISL6265A INTERNAL CIRCUIT
IL
L
DCR
INDUCTOR
VL(s)
VC(s)
R1
C1
R2
VOUT
COUT
CURRENT
SENSE
RNTC OPTIONAL
ISP
NTC
R3 NETWORK
ISN
FIGURE 9. DCR SENSING COMPONENTS
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 9. The inductor current,
IL, flowing through the inductor, passes through the DCR.
Equation 6 shows the s-domain equivalent voltage, VL,
across the inductor.
VL(s) = IL ⋅ (s L + DCR)
(EQ. 6)
A simple R-C network across the inductor (R1, R2 and C)
extracts the DCR voltage, as shown in Equation 7. The
voltage across the sense capacitor, VC, can be shown to be
proportional to the output current IL, shown in Equation 7.
--s--------L---
DCR
+
1⎠⎞
VC(s)
=
----------------------------------------------------------
s
(---R-----1-------R-----2---)
R1 + R2
C1
+
1
K
DCR
IL
(EQ. 7)
Where:
K
=
-------R-----2--------
R2 + R1
(EQ. 8)
Sensing the time varying inductor current accurately
requires that the parallel R-C network time constant match
the inductor L/DCR time constant. If the R-C network
components are selected, such that the R-C time constant
matches the inductor L/DCR time constant (see Equation 9),
then VC is equal to the voltage drop across the DCR
multiplied by the ratio of the resistor divider, K.
------L-------
DCR
=
-R-----1-------R-----2--
R1 + R2
C1
(EQ. 9)
The inductor current sense information is used for current
balance in dual plane applications, overcurrent detection in
core outputs and output voltage droop depending on
controller configuration.
CORE DCR TEMPERATURE COMPENSATION
It may also be necessary to compensate for changes in
inductor DCR due to temperature. DCR shifts due to
temperature cause time constant mismatch, skewing inductor
current accuracy. Potential problems include output voltage
droop and OC trip point, both shifting significantly from
expected levels. The addition of a negative temperature
coefficient (NTC) resistor to the R-C network compensates for
the rise in DCR due to temperature. Typical NTC values are in
the 10kΩ range. A second resistor, R3, in series with the NTC
allows for more accurate time-constant and resistor-ratio
matching as the pair of resistors are placed in parallel with R2
(Figure 9). The NTC resistor must be placed next to the
inductor for good heat transfer, while R1, R2, R3, and C1 are
placed close to the controller for interference immunity.
CORE DCR COMPONENT SELECTION FOR DROOP
By adjusting the ratio between inductor DCR drop and the
voltage measured across the sense capacitor, the load line
can be set to any level, giving the converter the correct
amount of droop at all load currents.
Equation 10 shows the relation between droop voltage,
VDROOP
=
I--M-----A----X--
IOC
5
VC,
O
C
(EQ. 10)
maximum output current (IMAX), OC trip level and current
sense capacitor voltage at the OC current level, VC(OC).
AMD specifications do not require droop and provide no load
line guidelines. Tight static output voltage tolerance limits
push acceptable level of droop below a useful level for Griffin
applications. Care must be taken in applications which
implement droop to balance time constant mismatch, sense
capacitor resistor ratio, OC trip and droop equations.
Temperature shifts related to DCR must also be addressed,
as outlined in the previous section.
16
FN6884.0
May 11, 2009
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