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6265AHRTZ Просмотр технического описания (PDF) - Intersil

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6265AHRTZ Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs Intersil
Intersil Intersil
6265AHRTZ Datasheet PDF : 23 Pages
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ISL6265A
SVC
SVD
6 5 4 32 10
SLAVE ADDRESS PHASE
(See Table 3)
SVID
7 654 3 210
DATA PHASE
FIGURE 8. SEND BYTE EXAMPLE
SVI Bus Protocol
The AMD processor bus protocol is compliant with SMBus
send byte protocol for VID transactions (see Figure 8). During a
send byte transaction, the processor sends the start sequence
followed by the slave address of the VR for which the VID
command applies. The address byte must be configured
according to Table 4. The processor then sends the write bit.
After the write bit, if the ISL6265A receives a valid address
byte, it sends the acknowledge bit. The processor then sends
the PSI-L bit and VID bits during the data phase. The Serial VID
8-bit data field encoding is outlined in Table 5. If ISL6265A
receives a valid 8-bit code during the data phase, it sends the
acknowledge bit. Finally, the processor sends the stop
sequence. After the ISL6265A has detected the stop, it can
then proceed with the VID-on-the-fly transition.
implement dynamic VID changes, and shutdown individual
outputs.
The ISL6265A controls the no-load output voltage of core and
Northbridge output to an accuracy of ±0.5% over-the-range of
0.75V to 1.5V. A fully differential amplifier implements core
voltage sensing for precise voltage control at the
microprocessor die.
Switching Frequency
The R3 modulator scheme is a variable frequency PWM
architecture. The switching frequency increases during the
application of a load to improve transient performance. It
also varies slightly due to changes in input and output
voltage and output current. This variation is normally less
than 10% in continuous conduction mode.
TABLE 4. SVI SEND BYTE ADDRESS DESCRIPTION
BITS
DESCRIPTION
6:4 Always 110b
3 Reserved by AMD for future use
2 VDD1, if set then the following data byte contains the VID for
VDD1
1 VDD0, if set then the following data byte contains the VID for
VID0
0 VDDNB, if set then the following data byte contains the VID
for VIDNB
TABLE 5. SERIAL VID 8-BIT DATA FIELD ENCODING
BITS
DESCRIPTION
7 PSI_L:
= 0 means the processor is at an optimal load for the
regulator(s) to enter power-savings mode
= 1 means the processor is not at an optimal load for the
regulator(s) to enter power-saving mode
6:0 SVID[6:0] as defined in Table 3.
Operation
After the start-up sequence, the ISL6265A begins regulating
the core and Northbridge output voltages to the pre-PWROK
metal VID programmed. The controller monitors SVI
commands to determine when to enter power-savings mode,
CORE FREQUENCY SELECTION
A resistor connected between the VW and COMP pins of the
Core segment of the ISL6265A adjusts the switching window
and therefore adjusts the switching frequency. The RFSET
resistor that sets up the switching frequency of the converter
operating in CCM can be determined using Equation 3,
where RFSET is in kΩ and the switching period is in ms.
Designs for 300kHz switching frequency would result in a
RFSET value of 6.81kΩ.
RFSET(kΩ) = (Periods) 0.4) × 2.33
(EQ. 3)
In discontinuous conduction mode (DCM), the ISL6265A
runs in period stretching mode.
NORTHBRIDGE FREQUENCY SELECTION
The Northbridge switching frequency to programmed by a
resistor connected from the FSET_NB pin to the GND pin.
The approximate PWM switching frequency is written as
shown in Equation 4:
FSW = K---------R-----F---1S----E----T----N----B--
(EQ. 4)
Estimating the value of RFSET_NB is written as shown in
Equation 5:
RFSET
=
----------1----------
K FSW
(EQ. 5)
Where FSW is the PWM switching frequency, RFSET_NB is
the programming resistor and K = 1.5 x 10-10.
15
FN6884.0
May 11, 2009
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