voltage planes reduces in-rush current during the soft-start
interval. At the end of the soft-start interval, the PGOOD
output transitions high indicating all output planes are within
If the EN input falls below the enable falling threshold, the
ISL6265A tri-states all outputs. PGOOD is pulled low with
the loss of EN. The Core and Northbridge planes will decay
based on output capacitance and load leakage resistance. If
bias to VCC falls below the POR level, the ISL6265A
responds in the same manner previously described. Once
VCC and EN rise above their respective rising thresholds,
the internal DAC circuitry re-acquires a pre-PWROK metal
VID code and the controller soft-starts.
In VFIX Mode, the SVC and SVD levels fixed external to the
controller through jumpers to either GND or VDDIO. These
inputs are not expected to change. In VFIX mode, the IC
decodes the SVC and SVD states per Table 2.
TABLE 2. VFIXEN VID CODES
OUTPUT VOLTAGE (V)
Once enabled, the ISL6265A begins to soft-start both Core
and Northbridge planes to the programmed VFIX level. The
internal soft-start circuitry slowly ramps the reference up to the
target value. The same fixed internal rate of approximately
2mV/µs results in a controlled ramp of the power planes.
Once soft-start has ended and all output planes are within
regulation limits, the PGOOD pin transitions high.
In the same manner described in “Pre-PWROK Metal VID”
on page 12, the POR circuitry impacts the internal driver
operation and PGOOD status.
Once the controller has successfully soft-started and
PGOOD transitions high, the processor can assert PWROK
to signal the ISL6265A to prepare for SVI commands. The
controller actively monitors the SVI interface for set VID
commands to move the plane voltages to start-up VID
values. Details of the SVI Bus protocol are provided in the
AMD Design Guide for Voltage Regulator Controllers
Accepting Serial VID Codes specification.
Once a set VID command is received, the ISL6265A decodes
the information to determine which output plane is affected
and the VID target required (see Table 3).The internal DAC
circuitry steps the required output plane voltage to the new
VID level. During this time, one or more of the planes could be
targeted. In the event either core voltage plane, VDD0 or
VDD1, is commanded to power-off by serial VID commands,
the PGOOD signal remains asserted. The Northbridge
voltage plane must remain active during this time.
If the PWROK input is deasserted, then the controller steps
both Core and Northbridge planes back to the stored
pre-PWROK metal VID level in the holding register from
initial soft-start. No attempt is made to read the SVC and
SVD inputs during this time. If PWROK is reasserted, then
the on-board SVI interface waits for a set VID command.
If EN goes low during normal operation, all internal drivers
are tri-stated and PGOOD is pulled low. This event clears
the pre-PWROK metal VID code and forces the controller to
check SVC and SVD upon restart.
A POR event on VCC during normal operation will shutdown
all regulators and PGOOD is pulled low. The pre-PWROK
metal VID code is not retained.
Once PWROK is high, the ISL6265A detects this flag and
begins monitoring the SVC and SVD pins for SVI
instructions. The microprocessor will follow the protocol
outlined in the following sections to send instructions for
VID-on-the-Fly transitions. The ISL6265A decodes the
instruction and acknowledges the new VID code. For VID
codes higher than the current VID level, the ISL6265A
begins stepping the required regulator output(s) to the new
VID target with a typical slew rate of 7.5mV/µs, which meets
the AMD requirements.
When the VID codes are lower than the current VID level,
the ISL6265A begins stepping the regulator output to the
new VID target with a typical slew rate of -7.5mV/µs. Both
Core and NB regulators are always in CCM during a down
VID transition. The AMD requirements under these
conditions do not require the regulator to meet the minimum
slew rate specification of -5mV/µs. In either case, the slew
rate is not allowed to exceed 10mV/µs. The ISL6265A does
not change the state of PGOOD (VDDPWRGD in AMD
specifications) when a VID-on-the-fly transition occurs.
SVI WIRE Protocol
The SVI wire protocol is based on the I2C bus concept. Two
wires (serial clock (SVC) and serial data (SVD)), carry
information between the AMD processor (master) and VR
controller (slave) on the bus. The master initiates and
terminates SVI transactions and drives the clock, SVC,
during a transaction. The AMD processor is always the
master and the voltage regulators are the slaves. The slave
receives the SVI transactions and acts accordingly. Mobile
SVI wire protocol timing is based on high-speed mode I2C.
See AMD Griffin (Family 11h) processor publications for
May 11, 2009